Beyond Brown

When brown just isn't enough

Atari ST (and compatibles) IKBD ROM disassembly

* f9dasm: M6800/1/2/3/8/9 / H6309 Binary/OS9/FLEX9 Disassembler V1.75
* Loaded binary file IKBD.BIN
* Commented by The Paranoid of Paradox 2018/2019
*
*************************************************************************
** Hardware port usage by Atari                                         *
** Jankowski, Rabich, Reschke: Atari ST/STE/TT Profibuch,               *
** 11. Auflage 1992, SYBEX Verlag, Abb.7.7, p.962 and Abb.7.11, p.967   *
**                                                                      *
**  r0 <- [  ][F1][F2][F3][F4][F5][F6][F7][F8][F9][F0][he][un][ (][ /]  *
**  r1 <- [  ][  ][  ][  ][es]["2][$4][&6][(8][=0][´'][bs][up][ )][ *]  *
**  r2 <- [  ][  ][  ][  ][!1][§3][%5][/7][)9][?ß][^#][de][cl][ 7][ 9]  *
**  r3 <- [  ][  ][  ][  ][ta][ W][ R][ Z][ U][ O][ü@][in][le][ 8][ -]  *
**  r4 <- [co][  ][  ][  ][ Q][ E][ T][ G][ I][ P][*+][|~][do][ 4][ 6]  *
**  r5 <- [  ][ls][  ][  ][ A][ S][ F][ H][ J][ L][ö[][re][ri][ 5][ +]  *
**  r6 <- [  ][  ][al][  ][><][ D][ C][ B][ K][,;][.:][ä]][ 1][ 2][ 3]  *
**  r7 <- [  ][  ][  ][rs][ Y][ X][ V][ N][ M][sp][ca][-_][ 0][ .][en]  *
**         |   |   |   |   |   |   | __| __| __| __| __| __| __| __|    *
**         |   |   |   |   |   |   |   |   |   |   |   |   |   |   |    *
**  __p30_p31_p32_p33_p34_p35_p36_p37_p40_p41_p42_p43_p44_p45_p46_p47_  *
** |                                                                  | *
** |                             HD6301V1                             | *
** |                   128 Bytes RAM, 4096 Bytes ROM                  | *
** |                                                                  | *
** |______________p20_p21_p22_p23_p24_p10_p11_p12_p13_p14_p15_p16_p17_| *
**                 |   |   |   |   |   |   |   |   |   |   |   |   |    *
**           Trigger   |  _|_  |   |  r0  r1  r2  r3  r4  r5  r6  r7    *
**     74LS244-Latch MlB |   | RxD TxD                                  *
**                      MrB JfB                M=Mouse, J=Joystick      *
** _74LS244 connects______________             L=left, r=right, u=up,   *
** p40 p41 p42 p43 p44 p45 p46 p47 : HD6301    d=down, f=fire, B=button *
** MXb MXa MYa MYb  Ju  Jd  Jl  Jr : extern    RxD/TxD=receive/transmit *
**                                                                      *
** Interpretation of mouse movement (rising edge counts):               *
**              ____      ____      _________      ____      ____       *
**  MXa(MYa) __|    |____|    |____|         |____|    |____|    |__    *
**                ____      ____      _____      ____      ____         *
**  MXb(MYb) ____|    |____|    |____|     |____|    |____|    |____    *
**                                      |                               *
**             <-positive direction->  change   <-negative direction->  *
*************************************************************************
** Used Labels                                                          *
*************************************************************************
*
;
; Hardware registers
;
P1DDR   EQU     $0000    ; 6301 HW-Reg Port 1 Direction Register
P2DDR   EQU     $0001    ; 6301 HW-Reg Port 2 Direction Register
P1DAT   EQU     $0002    ; 6301 HW-Reg Port 1 Data Register
P2DAT   EQU     $0003    ; 6301 HW-Reg Port 2 Data Register
P3DDR   EQU     $0004    ; 6301 HW-Reg Port 3 Direction Register
P4DDR   EQU     $0005    ; 6301 HW-Reg Port 4 Direction Register
P3DAT   EQU     $0006    ; 6301 HW-Reg Port 3 Data Register
P4DAT   EQU     $0007    ; 6301 HW-Reg Port 4 Data Register
TCSR    EQU     $0008    ; 6301 HW-Reg Timer Control/Status Register
FRCH    EQU     $0009    ; 6301 HW-Reg Free Runing Counter High Byte
OCRH    EQU     $000B    ; 6301 HW-Reg Output Compare High Byte
OCRL    EQU     $000C    ; 6301 HW-Reg Output Compare Low Byte
RMCR    EQU     $0010    ; 6301 HW-Reg Rate and Mode Control
TRCSR   EQU     $0011    ; 6301 HW-Reg Transmit/Receive Control/Status
RXB     EQU     $0012    ; 6301 HW-Reg Receive Buffer
TXB     EQU     $0013    ; 6301 HW-Reg Transmit Buffer
;
; Random access memory (RAM)
;
Cnt1ms  EQU     $0080    ; Counter for 1ms cycles
TodYr   EQU     $0082    ; Time of day: Year in BCD
TodMon  EQU     $0083    ; Time of day: Month in BCD
TodDay  EQU     $0084    ; Time of day: Day in BCD
TodHr   EQU     $0085    ; Time of day: Hour in BCD
TodMin  EQU     $0086    ; Time of day: Minute in BCD
TodSec  EQU     $0087    ; Time of day: Second in BCD
PrcLiv  EQU     $0088    ; "Process Lives" magic number ($AA)
M0089   EQU     $0089    ; Keyboard scanning bitfield:
                         ;   Bit 7: Ignore keyboard in 1ms ISR
                         ;   Bit 6:
                         ;   Bit 5: "Right shift" flag
                         ;   Bit 4: "Alternate" flag
                         ;   Bit 3: "Left Shift" flag
                         ;   Bit 2: "Control" flag
                         ;   Bit 1:
                         ;   Bit 0:
ColCnt  EQU     $008A    ; Keyboard column counter
M008B   EQU     $008B    ; Keyboard scan cycle index ($80, $01, $00, $02)
ColMsk  EQU     $008C    ; Mask to write to P3 and P4 for sanning keyboard
RowRaw  EQU     $008E    ; Keyboard row raw value
M008F   EQU     $008F    ; Table start: 
M0090   EQU     $0090    ;   Entry
M0091   EQU     $0091    ;   Entry
M0092   EQU     $0092    ;   Entry
M0093   EQU     $0093
JMonRR  EQU     $0094    ; Joystick monitoring rate reload
JKCodRx EQU     $0095    ; Data for joystick keycode mode: Rx
JKCodRy EQU     $0096    ; Data for joystick keycode mode: Ry
JKCodTx EQU     $0097    ; Data for joystick keycode mode: Tx
JKCodTy EQU     $0098    ; Data for joystick keycode mode: Ty
JKCodVx EQU     $0099    ; Data for joystick keycode mode: Vx
JKCodVy EQU     $009A    ; Data for joystick keycode mode: Vy
MBfP2   EQU     $009B    ; Mouse buttons copied directly from P2 (bits 1/2)
M009C   EQU     $009C    ; Mouse buttons, initial value for debouncing
M009D   EQU     $009D    ; Cycle counter to read in mouse buttons (0..10)
M009E   EQU     $009E    ; Counter
M009F   EQU     $009F
M00A0   EQU     $00A0
M00A1   EQU     $00A1    ; Control bitfield:
                         ;   Bit 7: Joystick keycode mode disable
                         ;   Bit 6:
                         ;   Bit 5:
J0KCodC EQU     $00A2    ; Joystick 0 counter to generate keycode data
J1KCodC EQU     $00A3    ; Joystick 1 counter to generate keycode data
J0Data  EQU     $00A4    ; Joystick 0 data: x000 yyyy (x=button,y=pos.)
J1Data  EQU     $00A5    ; Joystick 1 data: x000 yyyy (x=button,y=pos.)
M00A6   EQU     $00A6    ; Counter (10..0)
JMonRC  EQU     $00A7    ; Joystick monitoring rate counter
M00A8   EQU     $00A8
M00A9   EQU     $00A9
MAbMaxX EQU     $00AA    ; Mouse absolute max.X pos. ($00AA=MSB, $00AB=LSB)
MAbMaxY EQU     $00AC    ; Mouse absolute max.Y pos. ($00AC=MSB, $00AD=LSB)
MKCodDx EQU     $00AE    ; Mouse keycode mode DeltaX
MKCodDy EQU     $00AF    ; Mouse keycode mode DeltaY
MEvThrX EQU     $00B0    ; Mouse event threshold X
MEvThrY EQU     $00B1    ; Mouse event threshold Y
MAbsScX EQU     $00B2    ; Mouse absolute positioning mode, scale X
MAbsScY EQU     $00B3    ; Mouse absolute positioning mode, scale Y
MBActn  EQU     $00B4    ; Configuration bitfield of mouse button action
                         ;   Bit 2: Operation mode (Keycode mode = 1)
                         ;   Bit 1: Button release causes event report
                         ;   Bit 0: Button down causes event report
MBEvnt  EQU     $00B5    ; Presumed mouse button data for IKBD command $0D
                         ;   Bit 3: Left button up since last report
                         ;   Bit 2: Left button down since last report
                         ;   Bit 1: Right button up since last report
                         ;   Bit 0: Right button down since last report
MXCoord EQU     $00B6    ; Mouse X coordinate ($00B6 = MSB, $00B8 = LSB)
MYCoord EQU     $00B8    ; Mouse Y coordinate ($00B8 = MSB, $00B9 = LSB)
M00BA   EQU     $00BA
M00BB   EQU     $00BB
MRelDx  EQU     $00BC    ; Mouse relative position Delta_X
MRelDy  EQU     $00BD    ; Mouse relative position Delta_Y
MXraw   EQU     $00BE    ; Mouse Xb/Xa raw pin data (bits 0/1)
MYraw   EQU     $00BF    ; Mouse Ya/Yb raw pin data (bits 0/1)
MBraw   EQU     $00C0    ; Mouse lB/rB raw pin data (bits 1/2)
MBStat  EQU     $00C1    ; Mouse button status bitfield:
                         ;   Bit 3: Left mouse button previous
                         ;   Bit 2: Left mouse button current
                         ;   Bit 1: Right mouse button previous
                         ;   Bit 0: Right mouse button current
M00C2   EQU     $00C2    ; Mouse button action since last interrogation
M00C3   EQU     $00C3    ; Presumed mouse x configuration
M00C4   EQU     $00C4    ; Presumed mouse y configuration
M00C5   EQU     $00C5    ; Mouse buttons in bits 1 and 2 (0x02/0x04)
M00C6   EQU     $00C6    ; Bitfield, partially directly from 74LS244:
                         ;   Bit 7:
                         ;   Bit 6:
                         ;   Bit 3: MyB
                         ;   Bit 2: MyA
                         ;   Bit 1: MxA/Mouse event occured (negative)
                         ;   Bit 0: MxB/Mouse event occured (positive)
MAccHi  EQU     $00C7    ; Accumulator to calculate relative mouse...
MAccLo  EQU     $00C8    ; ...coordinates (MSB=$00C7, LSB=$00C8)
MMode   EQU     $00C9    ; Mouse control bitfield (Init: #$98)
                         ;   Bit 0: Y=0 at top/bottom
                         ;   Bit 1: Fire button monitoring no/yes
                         ;   Bit 3: Output disabled/enabled
                         ;   Bit 4: Mouse relative position reporting
                         ;   Bit 5: Mouse absolute position reporting
                         ;   Bit 6: Mouse keycode mode
                         ;   Bit 7: Mouse disabled/enabled
JMode   EQU     $00CA    : Joystick control bitfield (Init: #$28)
                         ;  Bit 7: Joystick 0 data valid
                         ;  Bit 6: Joystick 1 data valid
                         ;  Bit 5: Joystick evaluation active flag
                         ;  Bit 4: Joystick interrogation mode
                         ;  Bit 3: Joystick event reporting mode
                         ;  Bit 2: Joystick keycode mode
                         ;  Bit 1: Joystick monitoring mode
                         ;  Bit 0: Fire button monitoring mode
M00CB   EQU     $00CB    ; Serial receive configuration bitfield:
                         ;  Bit    7: First Byte received (IKBD command)
                         ;  Bit    6: Receive buffer exhausted (?)
                         ;  Bit    5:
                         ;  Bit    4:
                         ;  Bit    3:
                         ;  Bit 2..0:
RxCnt   EQU     $00CC    ; Serial receive byte count
RxDat0  EQU     $00CD    ; Serial receive buffer byte[0]
RxDat1  EQU     $00CE    ; Serial receive buffer byte[1]
RxDat2  EQU     $00CF    ; Serial receive buffer byte[2]
RxDat3  EQU     $00D0    ; Serial receive buffer byte[3]
RxDat4  EQU     $00D1    ; Serial receive buffer byte[4]
RxDat5  EQU     $00D2    ; Serial receive buffer byte[5]
RxDat6  EQU     $00D3    ; Serial receive buffer byte[6]
RxErr   EQU     $00D4    ; Seems to count serial overrun/framing errors
TxNo    EQU     $00D5    ; Counter for generating serial transmissions
TxCnt   EQU     $00D6    ; Serial transmit byte count
M00D7   EQU     $00D7    ; Serial transmit control byte (Init: $95)
                         ;   Bit    7: Overflow flag (?)
                         ;   Bit 4..0: Counter (limited to 21)
TxLim   EQU     $00D8    ; Number of bytes to be transmit
TxDat0  EQU     $00D9    ; Serial transmit buffer byte[0]
MemPnt  EQU     $00EE    ; Temporary Pointer for IKBD (Mem.load/read/exc.)
MemCnt  EQU     $00F0    ; Temporary Counter for IKBD (Mem.load only)


*****************************************************
** Program Code / Data Areas                        *
*****************************************************

        ORG     $F000
;
; Actually, the reset vector points here (and various others),
; So this is where the software actually starts to run.
;
; It first checks for a "process lives" ($AA) mark at $0088
;        
hdlr_RST
        LDAA    PrcLiv                   *F000: 96 88    ; Check mem...
        CMPA    #$AA                     *F002: 81 AA    ; ...for magic no.
        BEQ     ZF010                    *F004: 27 0A    ; If found, skip
        LDD     #$0080                   *F006: CC 00 80 ; Else, load addr.
        BRA     ZF014                    *F009: 20 09    ; Branch to below
ZF00B   TIM     #$01,TRCSR               *F00B: 7B 01 11 ; Check for WU-Bit
        BNE     ZF00B                    *F00E: 26 FB    ; If set, loop
ZF010   SEI                              *F010: 0F       ; Block all IRQs
        LDD     #$0089                   *F011: CC 00 89 ; Set D to $0089
;
; Initialize stack, ports and serial configurations registers
ZF014   LDS     #$00FF                   *F014: 8E 00 FF ; Initialize Stack
        CLRA                             *F017: 4F       ; Clear AccA
        STAA    P1DDR                    *F018: 97 00    ; Set P1 to all in
        INCA                             *F01A: 4C       ; Set AccuA to $01
        STAA    P2DAT                    *F01B: 97 03    ; Set P2.0 to "1"
        STAA    P2DDR                    *F01D: 97 01    ; Set P2.0 to out
        LDX     #$FFFF                   *F01F: CE FF FF ; Set X to All-1s
        STX     P3DAT                    *F022: DF 06    ; Set all P3 to 1
        STX     P3DDR                    *F024: DF 04    ; Make P3 all out
        LDAA    #$05                     *F026: 86 05    ; Set AccA to $05
        STAA    RMCR                     *F028: 97 10    ; Set serial conf.
        LDAA    #$1A                     *F02A: 86 1A    ; Set AccA to $1A
        STAA    TRCSR                    *F02C: 97 11    ; Set serial CSR
        LDAA    TRCSR                    *F02E: 96 11    ; Read back
        LDAA    RXB                      *F030: 96 12    ; Empty RxBuf
        CMPB    #$89                     *F032: C1 89    ; Check AccB
        BEQ     ZF048                    *F034: 27 12    ; If equal, branch
        CLRA                             *F036: 4F       ; Else, clear AccA
;
; Wait loop
ZF037   DECA                             *F037: 4A       ; Decrease AccA
        NOP                              *F038: 01       ; Wait
        BNE     ZF037                    *F039: 26 FC    ; If not 0, loop
; 
        OIM     #$01,TRCSR               *F03B: 72 01 11 ; Set WU-Bit
        LDAA    #$20                     *F03E: 86 20    ; Set AccA to $20
;
; Wait some more
ZF040   DECA                             *F040: 4A       ; Decrease AccA
        BNE     ZF040                    *F041: 26 FD    ; If not 0, loop
;
; Now wait until WU-Bit is reset
ZF043   TIM     #$01,TRCSR               *F043: 7B 01 11 ; Check for WU-Bit
        BNE     ZF043                    *F046: 26 FB    ; If set, loop
;
; Enable Output Compare Interrupt
ZF048   LDAA    #$08                     *F048: 86 08    ; Set AccA to $08
        STAA    TCSR                     *F04A: 97 08    ; Enable OC-IRQ
;
; Set all RAM to $5A (AccB is still $80 or $88 from above)
ZF04C   LDAA    #$5A                     *F04C: 86 5A    ; Load $5A to AccA
ZF04E   LDX     #$0000                   *F04E: CE 00 00 ; Reset X
        ABX                              *F051: 3A       ; Add AccB to X
ZF052   STAA    ,X                       *F052: A7 00    ; Store A->(mem)X
        INX                              *F054: 08       ; Increase X
        CPX     #$0100                   *F055: 8C 01 00 ; Check if $0100
        BNE     ZF052                    *F058: 26 F8    ; If not, loop
;
; Now check all RAM (AccB is still $80 or $88 from above)
        LDX     #$0000                   *F05A: CE 00 00 ; Reset IndexX
        ABX                              *F05D: 3A       ; Add AccB to X
ZF05E   CMPA    ,X                       *F05E: A1 00    ; Compare to mem.
        BNE     ZF04C                    *F060: 26 EA    ; No match? Repeat
        INX                              *F062: 08       ; Increase X
        CPX     #$0100                   *F063: 8C 01 00 ; Check if $0100
        BNE     ZF05E                    *F066: 26 F6    ; If not, loop
;
; Was AccA $A5? If so, exit, if not, set AccA to $A5 and repeat RAM test
        CMPA    #$A5                     *F068: 81 A5    ; Compare A to $A5
        BEQ     ZF070                    *F06A: 27 04    ; If equal, branch
        LDAA    #$A5                     *F06C: 86 A5    ; Set AccA to $A5
        BRA     ZF04E                    *F06E: 20 DE    ; Repeat mem.test
;
; Now test if checksum for ROM ($F000..$FF6E and $FFF0..$FFFF) is zero
ZF070   CLRA                             *F070: 4F       ; Reset AccA
        LDX     #$F000                   *F071: CE F0 00 ; Set X=ROM start
ZF074   ADCA    ,X                       *F074: A9 00    ; Add (mem)X to A
        INX                              *F076: 08       ; Increase X
        BEQ     ZF083                    *F077: 27 0A    ; Branch if zero
        CPX     #$FF6F                   *F079: 8C FF 6F ; Is X = $FF6F?
        BNE     ZF074                    *F07C: 26 F6    ; If not, loop
        LDX     #$FFF0                   *F07E: CE FF F0 ; Set X to $FFF0
        BRA     ZF074                    *F081: 20 F1    ; Loop
ZF083   COMA                             *F083: 43       ; Invert AccA
        BNE     ZF04C                    *F084: 26 C6    ; If not 0, repeat
;
; Test the keyboard: Activate each column (P3+P4), read back rows (P1).
        LDAB    #$01                     *F086: C6 01    ; Set AccB to $01
        STAB    COlCnt                   *F088: D7 8A    ; Store in mem.
        CLRA                             *F08A: 4F       ; Clear AccA
        INCB                             *F08B: 5C       ; Increase AccB
ZF08C   STD     ColMsk                   *F08C: DD 8C    ; Store both
        COMA                             *F08E: 43       ; Invert AccA
        COMB                             *F08F: 53       ; Invert AccB
        STAB    P3DAT                    *F090: D7 06    ; Outout B at P3
        STAA    P4DAT                    *F092: 97 07    ; Output A to P4
        LDAA    P1DAT                    *F094: 96 02    ; Read In P1 to A
        COMA                             *F096: 43       ; Invert AccA
        BNE     ZF0A3                    *F097: 26 0A    ; If !=0, branch
ZF099   INC     >ColCnt                  *F099: 7C 00 8A ; Inc. byte at $8A
        LDD     ColMsk                   *F09C: DC 8C    ; Load D from mem
        ASLD                             *F09E: 05       ; Shift D left
        BCC     ZF08C                    *F09F: 24 EB    ; No carry? Branch
        BRA     ZF0CF                    *F0A1: 20 2C    ; Branch to below
;
; Key presumed stuck - For columns 1..4, special treatment required
ZF0A3   LDAB    ColCnt                   *F0A3: D6 8A    ; Load mem to AccB
        CMPB    #$05                     *F0A5: C1 05    ; Check B for $05
        BCC     ZF0BA                    *F0A7: 24 11    ; If above, branch
        BITA    #$01                     *F0A9: 85 01    ; Test Bit 0 in A
        BNE     ZF0BA                    *F0AB: 26 0D    ; If !=0, branch
        BITA    #$F0                     *F0AD: 85 F0    ; Test high nibble
        BEQ     ZF099                    *F0AF: 27 E8    ; If zero,continue
        DECB                             *F0B1: 5A       ; Decrease B
        LDX     #MF206                   *F0B2: CE F2 06 ; Load addr. to X
        ABX                              *F0B5: 3A       ; Add AccB to X
        LDAA    ,X                       *F0B6: A6 00    ; Load mem(X) to A
        BRA     ZF0C5                    *F0B8: 20 0B    ; Branch to below
;
; Key presumed stuck - Decode scancode
ZF0BA   LDAB    #$01                     *F0BA: C6 01    ; Set AccB to $01
; The following 2 bytes can be interpreted in two different ways:
        TST     $58,X                    *F0BC: 6D 58    ; Test (mem+X)
; Or, if being branched to from $F0BF:
        FCB     $6D                      *F0BC: 6D       ; Data '.'
        ASLB                             *F0BD: 58       ; Multiply B by 2
; Code continues here in any of these two cases
        LSRA                             *F0BE: 44       ; Shift AccA right
        BCC     ZF0BD                    *F0BF: 24 FC    ; No carry? Loop
        TBA                              *F0C1: 17       ; AccB -> AccA
        JSR     ZF2F7                    *F0C2: BD F2 F7 ; Subroutine
;
; This snippets sends a "break" code of the key detected stuck
ZF0C5   ORAA    #$80                     *F0C5: 8A 80    ; Set AccA bit 7
ZF0C7   LDAB    TRCSR                    *F0C7: D6 11    ; Load TRCSR
        BITB    #$20                     *F0C9: C5 20    ; Check TDRE
        BEQ     ZF0C7                    *F0CB: 27 FA    ; Loop if clear
        STAA    TXB                      *F0CD: 97 13    ; Transmit AccA
;
; Terminate the keyboard test
ZF0CF   LDD     #$FFFF                   *F0CF: CC FF FF ; Now set P3+P4...
        STD     P3DAT                    *F0D2: DD 06    ; ...to all Ones
;
; Wait for TDRE to be set, then send IKBD Sofware version ($F0, $F1, ...)
ZF0D4   LDAA    TRCSR                    *F0D4: 96 11    ; Fetch TRCSR
        BITA    #$20                     *F0D6: 85 20    ; Check TDRE
        BEQ     ZF0D4                    *F0D8: 27 FA    ; Loop if clear
        LDAA    #$F1                     *F0DA: 86 F1    ; Software Version
        STAA    TXB                      *F0DC: 97 13    ; to be sent
;
; This part clears RAM, either all RAM or from behind magic number at $0088
        CLRA                             *F0DE: 4F       ; Reset AccA
        LDX     #0000                    *F0DF: CE 00 00 ; Reset X
        LDAB    TodYr                    *F0E2: D6 82    ; Read mem to AccB
        CMPB    #$A5                     *F0E4: C1 A5    ; Is it Magic No?
        BNE     ZF0EC                    *F0E6: 26 04    ; If not, skip
        LDAB    #$80                     *F0E8: C6 80    ; If, set B to $80
        BRA     ZF0EE                    *F0EA: 20 02    ; And skip next
ZF0EC   LDAB    #$89                     *F0EC: C6 89    ; Set AccB=$89
ZF0EE   ABX                              *F0EE: 3A       ; Add AccB to X
ZF0EF   STAA    ,X                       *F0EF: A7 00    ; Store AccA at X
        INX                              *F0F1: 08       ; Increase X
        CPX     #$0100                   *F0F2: 8C 01 00 ; Check for limit
        BNE     ZF0EF                    *F0F5: 26 F8    ; Loop until reached
;
; Basic initialisation of the RAM variables
        LDAB    #$AA                     *F0F7: C6 AA    ; Load "Alive"-Flag
        STAB    PrcLiv                   *F0F9: D7 88    ; Store at MagicNo
        LDAB    #$80                     *F0FB: C6 80    ; Load init value
        STAB    M008B                    *F0FD: D7 8B    ; Store at $008B
        LDAB    #$01                     *F0FF: C6 01    ; Init AccB with 1
        STAB    ColCnt                   *F101: D7 8A    ; Store at $008A
        INCB                             *F103: 5C       ; Inc. AccB to 2
        STD     ColMsk                   *F104: DD 8C    ; Store D at $008C
        INCA                             *F106: 4C       ; Inc. AccA to 1
        STAA    MEvThrX                  *F107: 97 B0    ; Store at $00B0
        STAA    MEvThrY                  *F109: 97 B1    ; Store at $00B1
        STAA    MAbsScX                  *F10B: 97 B2    ; Store at $00B2
        STAA    MAbsScY                  *F10D: 97 B3    ; Store at $00B3
        LDAA    #$98                     *F10F: 86 98    ; Load $98 to AccA
        STAA    MMode                    *F111: 97 C9    ; Store at $00C9
        LDAA    #$28                     *F113: 86 28    ; Load $28 to AccA
        STAA    JMode                    *F115: 97 CA    ; Store at $00CA
        LDAA    #$06                     *F117: 86 06    ; Load $06 to AccA
        STAA    MBfP2                    *F119: 97 9B    ; Store at $009B
        LDAA    #$95                     *F11B: 86 95    ; Load $95 to AccA
        STAA    M00D7                    *F11D: 97 D7    ; Store at $00D7
;
; Initial read of mouse and joystick data via 74LS244
        LDAA    #$FE                     *F11F: 86 FE    ; Load $FE to AccA
        STAA    P2DAT                    *F121: 97 03    ; Write as P2 Data
        CLRA                             *F123: 4F       ; Configure P4...
        STAA    P4DDR                    *F124: 97 05    ; ...to all input
        JSR     ZFB8E                    *F126: BD FB 8E ; Read mouse/joyst
;
; Check how close FRCH/FRCL are to OCRH/OCRL, then initialize time base
        LDD     FRCH                     *F129: DC 09    ; Fetch Counter
        ADDB    #$13                     *F12B: CB 13    ; Add to low byte
        CMPB    OCRL                     *F12D: D1 0C    ; against CompReg
        BNE     ZF132                    *F12F: 26 01    ; Skip if not equal
        NOP                              *F131: 01       ; if, do nothing
ZF132   LDD     FRCH                     *F132: DC 09    ; Fetch Counter
        ADDD    #$0010                   *F134: C3 00 10 ; Add 16
        STD     OCRH                     *F137: DD 0B    ; Write to Compare
        CLI                              *F139: 0E       ; Allow Interrupts
;
; This is a bit like the entry to the main loop
; It is being referenced multiple times from below (Bcc and JMP)
ZF13A   LDAA    M00CB                    *F13A: 96 CB    ; Read to AccA
        BPL     ZF141                    *F13C: 2A 03    ; Skip the JSR...
        JSR     ZF8D4                    *F13E: BD F8 D4 ; ...if positive
ZF141   LDAB    MMode                    *F141: D6 C9    ; Read to AccB
        BITB    #$02                     *F143: C5 02    ; Check Bit1 of B
        BNE     ZF171                    *F145: 26 2A    ; If not set, skip
        TSTB                             *F147: 5D       ; Test B for N+Z
        BPL     ZF157                    *F148: 2A 0D    ; Go ahead if pos.
        JSR     ZF186                    *F14A: BD F1 86 ; Call subroutine
        JMP     ZF371                    *F14D: 7E F3 71 ; And jump ahead
;
; Additional entry point, being branched to multiple times
ZF150   LDAA    M00CB                    *F150: 96 CB    ; Read to AccA
        BPL     ZF171                    *F152: 2A 1D    ; Go ahead if pos.
        JSR     ZF8D4                    *F154: BD F8 D4 ; Call subroutine
ZF157   TIM     #$20,JMode               *F157: 7B 20 CA ; Test mem for $20
        BEQ     ZF13A                    *F15A: 27 DE    ; If zero, go up
        LDAA    MMode                    *F15C: 96 C9    ; Read to AccA
        BPL     ZF16B                    *F15E: 2A 0B    ; Go ahead if pos.
ZF160   LDAA    P4DAT                    *F160: 96 07    ; Read P4Dat to A
        CMPA    P4DAT                    *F162: 91 07    ; Check with P4Dat
        BNE     ZF160                    *F164: 26 FA    ; Mismatch? Repeat
        ANDA    #$F0                     *F166: 84 F0    ; Mouse data only
        JMP     ZF681                    *F168: 7E F6 81 ; Jump to eval.
ZF16B   JSR     ZF186                    *F16B: BD F1 86 ; Call subroutine
        JMP     ZF681                    *F16E: 7E F6 81 ; Jump to eval.
ZF171   LDAA    JMode                    *F171: 96 CA    ; Read to AccA
        BITA    #$20                     *F173: 85 20    ; Test Bit 5
        BEQ     ZF13A                    *F175: 27 C3    ; Go back if clr
        BITA    #$03                     *F177: 85 03    ; Test Bit 0,1
        BEQ     ZF16B                    *F179: 27 F0    ; If clr, go back
        TIM     #$08,M00CB               *F17B: 7B 08 CB ; Test Mem. & $08
        BNE     ZF13A                    *F17E: 26 BA    ; If set, go back
        LSRA                             *F180: 44       ; Shift AccA right
        BCC     ZF16B                    *F181: 24 E8    ; No carry? Go up
        JMP     ZF8A2                    *F183: 7E F8 A2 ; Otherwise, jump
;
; Subroutine to debounce mouse/joystick buttons and read 74LS244 latch
; It also returns the current content of the 74LS244 in AccA
ZF186   LDAA    P2DAT                    *F186: 96 03    ; Fetch P2Dat to A
        CMPA    P2DAT                    *F188: 91 03    ; Check with P2Dat
        BNE     ZF186                    *F18A: 26 FA    ; Mismatch? Repeat
        ANDA    #$06                     *F18C: 84 06    ; Buttons only
        LDAB    M009D                    *F18E: D6 9D    ; Read mem to AccB
        BEQ     ZF1A7                    *F190: 27 15    ; If zero, go down
        CMPB    #$0A                     *F192: C1 0A    ; Check for $0A
        BCS     ZF1B0                    *F194: 25 1A    ; If lower, branch
        CLRB                             *F196: 5F       ; Clear AccB
        STAB    M009D                    *F197: D7 9D    ; Store to mem.
        STAA    M00C5                    *F199: 97 C5    ; Store buttons
        TAB                              *F19B: 16       ; Copy A->B
        EORA    M009C                    *F19C: 98 9C    ; XOR A with mem.
        ANDA    MBfP2                    *F19E: 94 9B    ; AND A with mem.
        ANDB    M009C                    *F1A0: D4 9C    ; AND B with mem.
        ABA                              *F1A2: 1B       ; Add A+B -> A
        STAA    MBfP2                    *F1A3: 97 9B    ; Store A in mem.
        LDAA    M00C5                    *F1A5: 96 C5    ; Read to AccA
ZF1A7   CMPA    MBfP2                    *F1A7: 91 9B    ; Compare A/mem
        BEQ     ZF1B0                    *F1A9: 27 05    ; If equal, skip
        STAA    M009C                    *F1AB: 97 9C    ; Store A in mem.
        INC     >M009D                   *F1AD: 7C 00 9D ; Add 1 to mem.
ZF1B0   LDAA    P4DAT                    *F1B0: 96 07    ; Read P4Dat to A
        CMPA    P4DAT                    *F1B2: 91 07    ; Check again
        BNE     ZF1B0                    *F1B4: 26 FA    ; Mismatch? Repeat
        RTS                              *F1B6: 39       ; Return
;
; Setup keyboard column, read row, restore configuration
ZF1B7   LDAA    #$01                     *F1B7: 86 01    ; Set latch...
        STAA    P2DAT                    *F1B9: 97 03    ; ...trigger high
        LDD     ColMsk                   *F1BB: DC 8C    ; Read mem to D
        COMA                             *F1BD: 43       ; Invert AccA
        COMB                             *F1BE: 53       ; Invert AccB
        STAB    P3DAT                    *F1BF: D7 06    ; Set column 1/2
        LDAB    #$FF                     *F1C1: C6 FF    ; Load AccB to...
        STAB    P4DDR                    *F1C3: D7 05    ; ..make P4 output
        STAA    P4DAT                    *F1C5: 97 07    ; Set column 2/2
ZF1C7   LDAA    P1DAT                    *F1C7: 96 02    ; Read row to AccA
        CMPA    P1DAT                    *F1C9: 91 02    ; Check
        BNE     ZF1C7                    *F1CB: 26 FA    ; Mismatch? Repeat
        LDX     #$FFFF                   *F1CD: CE FF FF ; Set P3 and P4...
        STX     P3DAT                    *F1D0: DF 06    ; ...to all ones
        LDAB    #$FE                     *F1D2: C6 FE    ; Set AccB to $FE
        STAB    P2DAT                    *F1D4: D7 03    ; Trigger latch
        CLRB                             *F1D6: 5F       ; Reset AccB
        STAB    P4DDR                    *F1D7: D7 05    ; Set P4 all input
        COMA                             *F1D9: 43       ; Invert AccA
        BNE     ZF1E3                    *F1DA: 26 07    ; Skip if not zero
        LDAB    M0089                    *F1DC: D6 89    ; Read mem to AccB
        BNE     ZF1E3                    *F1DE: 26 03    ; Skip if not zero
        JMP     ZF2D5                    *F1E0: 7E F2 D5 ; Jump otherwise
;
; Either a key is pressed now or has been recorded previously. Check out.
ZF1E3   STAA    RowRaw                   *F1E3: 97 8E    ; Store AccA
        LDAB    ColCnt                   *F1E5: D6 8A    ; Read mem to AccB
        CMPB    #$05                     *F1E7: C1 05    ; Check for $05(?)
        BCC     ZF240                    *F1E9: 24 55    ; Branch if higher
        DECB                             *F1EB: 5A       ; Decrease AccB
        LDX     #MF1FE                   *F1EC: CE F1 FE ; Load $F1FE to X
        ABX                              *F1EF: 3A       ; Add AccB to X
        LDAA    ,X                       *F1F0: A6 00    ; Read mem(X)->A
        STAA    M0093                    *F1F2: 97 93    ; Store in mem
        LDAB    #$04                     *F1F4: C6 04    ; Load 4 to AccB
        ABX                              *F1F6: 3A       ; Add AccB to X
        LDAA    ,X                       *F1F7: A6 00    ; Read mem(X)->A
        ABX                              *F1F9: 3A       ; Add AccB to X
        LDAB    ,X                       *F1FA: E6 00    ; Read mem(X)->B
        BRA     ZF20A                    *F1FC: 20 0C    ; Branch over tab.
;
; Table with masks for dedicated keys (goes to M0093)
MF1FE   FCB     $04                      *F1FE: 04       ; For ColCnt = 1
        FCB     $08                      *F1FF: 08       ; For ColCnt = 2
        FCB     $10                      *F200: 10       ; For ColCnt = 3
        FCB     $20                      *F201: 20       ; For ColCnt = 4
;
; Table with row masks for ctrl, lshift, alt and rshift (goes to AccA)
        FCB     $10                      *F202: 10       ; For ColCnt = 1
        FCB     $20                      *F203: 20       ; For ColCnt = 2
        FCB     $40                      *F204: 40       ; For ColCnt = 3
        FCB     $80                      *F205: 80       ; For ColCnt = 4
;
; Table with scancodes for ctrl, lshift, alt and rshift (goes to AccB)
MF206   FCB     $1D                      *F206: 1D       ; 'Control', Col 1
        FCB     $2A                      *F207: 2A       ; 'LShift', Col 2
        FCB     $38                      *F208: 38       ; 'Alt', Col 3
        FCB     $36                      *F209: 36       ; 'RShift', Col 4
;
; Interpret keyboard row for ColCnt 1..4 - start with ctrl, shift and alt
ZF20A   BITA    RowRaw                   *F20A: 95 8E    ; Bit (mem) in A?
        BEQ     ZF220                    *F20C: 27 12    ; If not, skip
        COMA                             *F20E: 43       ; Invert AccA
        ANDA    RowRaw                   *F20F: 94 8E    ; And A with mem
        STAA    RowRaw                   *F211: 97 8E    ; Store AccA again
        LDAA    M0093                    *F213: 96 93    ; Read mem to AccA
        BITA    M0089                    *F215: 95 89    ; Bit (mem) in A?
        BNE     ZF237                    *F217: 26 1E    ; If set, branch
        ORAA    M0089                    *F219: 9A 89    ; OR AccA and mem
        STAA    M0089                    *F21B: 97 89    ; Store result
        CLRA                             *F21D: 4F       ; Clear AccA
        BRA     ZF22F                    *F21E: 20 0F    ; Branch to below
ZF220   LDAA    M0089                    *F220: 96 89    ; Load mem to AccA
        BITA    M0093                    *F222: 95 93    ; Bit (mem) in A?
        BEQ     ZF237                    *F224: 27 11    ; If clear, branch
        LDAA    M0093                    *F226: 96 93    ; Load mem AccA
        COMA                             *F228: 43       ; Invert AccA
        ANDA    M0089                    *F229: 94 89    ; AND A with mem
        STAA    M0089                    *F22B: 97 89    ; Store there
        LDAA    #$80                     *F22D: 86 80    ; Load # to AccA
ZF22F   STAB    M0093                    *F22F: D7 93    ; Write B to mem
        ORAA    M0093                    *F231: 9A 93    ; OR this with A
        CLRB                             *F233: 5F       ; Clear AccB
        JSR     ZFD34                    *F234: BD FD 34 ; Subroutine
ZF237   LDAA    ColCnt                   *F237: 96 8A    ; Load mem to AccA
        CMPA    #$01                     *F239: 81 01    ; Is this a 1?
        BNE     ZF240                    *F23B: 26 03    ; If not, branch
        JMP     ZF2D5                    *F23D: 7E F2 D5 ; Jump to below
;
; Interpret keyboard for ColCnt > 4
ZF240   LDAA    TRCSR                    *F240: 96 11    ; Check serial...
        BITA    #$C0                     *F242: 85 C0    ; ...for RDRF+ORFE
        BEQ     ZF252                    *F244: 27 0C    ; If zero, branch
        BITA    #$40                     *F246: 85 40    ; Check ORFE only
        BEQ     ZF24F                    *F248: 27 05    ; If zero, branch
        JSR     ZFF40                    *F24A: BD FF 40 ; Subroutine,...
        BRA     ZF252                    *F24D: 20 03    ; ...then advance
ZF24F   JSR     ZFF04                    *F24F: BD FF 04 ; Rx-Subroutine
ZF252   LDAB    M008B                    *F252: D6 8B    ; Read mem to AccB
        BMI     ZF29A                    *F254: 2B 44    ; branch if neg.
        LDAA    #$01                     *F256: 86 01    ; Set AccA to 1
        LDAB    M0089                    *F258: D6 89    ; Load mem to AccB
        ANDB    #$03                     *F25A: C4 03    ; Only 2 low bits
        DECB                             *F25C: 5A       ; Decrease by 1
        CMPB    #$02                     *F25D: C1 02    ; Check if it's 2
        BNE     ZF26B                    *F25F: 26 0A    ; If not, go ahead
        CLRA                             *F261: 4F       ; If, clear AccA..
        CLRB                             *F262: 5F       ; ...and AccB...
        BRA     ZF26B                    *F263: 20 06    ; ...branch ahead
ZF265   LDAB    M0093                    *F265: D6 93    ; Read mem to AccB
        BNE     ZF2CF                    *F267: 26 66    ; Branch if not 0
        INCB                             *F269: 5C       ; Increase to '1'
        TBA                              *F26A: 17       ; Copy B->A
ZF26B   STAA    M0093                    *F26B: 97 93    ; Store A in mem
        LDX     #M0091                   *F26D: CE 00 91 ; Base address->X
        ABX                              *F270: 3A       ; Add B to X
        LDAA    ,X                       *F271: A6 00    ; Read mem(X)->A
        CMPA    ColCnt                   *F273: 91 8A    ; Compare with mem
        BNE     ZF265                    *F275: 26 EE    ; Go up if not eq.
        DEX                              *F277: 09       ; Otherwise, go...
        DEX                              *F278: 09       ; ...back 2 bytes
        LDAA    ,X                       *F279: A6 00    ; Load mem(X)->A
        BITA    RowRaw                   *F27B: 95 8E    ; Test mem on A
        BEQ     ZF286                    *F27D: 27 07    ; Branch if clear
        COMA                             *F27F: 43       ; Invert AccA
        ANDA    RowRaw                   *F280: 94 8E    ; AND A with mem
        STAA    RowRaw                   *F282: 97 8E    ; Store there
        BRA     ZF265                    *F284: 20 DF    ; Branch upwards
ZF286   INCB                             *F286: 5C       ; Increase AccB
        COMB                             *F287: 53       ; Invert AccB
        ANDB    M0089                    *F288: D4 89    ; AND B with mem
        STAB    M0089                    *F28A: D7 89    ; Store B there
        JSR     ZF2E8                    *F28C: BD F2 E8 ; Subroutine
        JSR     ZF2F7                    *F28F: BD F2 F7 ; Subroutine
        ORAA    #$80                     *F292: 8A 80    ; Set Bit 7 in A
        CLRB                             *F294: 5F       ; Clear AccB
        JSR     ZFD34                    *F295: BD FD 34 ; Subroutine
        BRA     ZF265                    *F298: 20 CB    ; Loop
;
ZF29A   LDAA    RowRaw                   *F29A: 96 8E    ; Fetch mem to A
        BEQ     ZF2D5                    *F29C: 27 37    ; If zero, go down
        LDAB    #$01                     *F29E: C6 01    ; Set AccB to 1
        BRA     ZF2A3                    *F2A0: 20 01    ; Skip next
ZF2A2   ASLB                             *F2A2: 58       ; Shift AccB left
ZF2A3   LSRA                             *F2A3: 44       ; Shift AccB right
        BCC     ZF2A2                    *F2A4: 24 FC    ; Loop if no carry
        TBA                              *F2A6: 17       ; Transfer B->A
        STAB    M0093                    *F2A7: D7 93    ; Store B there
        COMB                             *F2A9: 53       ; Invert AccB
        ANDB    RowRaw                   *F2AA: D4 8E    ; AND B with mem
        STAB    RowRaw                   *F2AC: D7 8E    ; Store B there
        LDAB    M008B                    *F2AE: D6 8B    ; Load mem to B
        ANDB    #$03                     *F2B0: C4 03    ; Only low 2 bits
        LDX     #M008F                   *F2B2: CE 00 8F : Fetch base addr.
        ABX                              *F2B5: 3A       ; Add B to X
        STAA    ,X                       *F2B6: A7 00    ; Store A there
        INX                              *F2B8: 08       ; Increase X...
        INX                              *F2B9: 08       ; ...twice
        LDAA    ColCnt                   *F2BA: 96 8A    ; Read mem to A
        STAA    ,X                       *F2BC: A7 00    ; Store A there
        INCB                             *F2BE: 5C       ; Increase AccB
        ORAB    M0089                    *F2BF: DA 89    ; OR B with mem
        STAB    M0089                    *F2C1: D7 89    ; Store B there
        JSR     ZF2E8                    *F2C3: BD F2 E8 ; Subroutine
        LDAA    M0093                    *F2C6: 96 93    ; Load mem to A
        JSR     ZF2F7                    *F2C8: BD F2 F7 ; Subroutine
        CLRB                             *F2CB: 5F       ; Clear AccB
        JSR     ZFD34                    *F2CC: BD FD 34 ; Subroutine
ZF2CF   LDAA    M008B                    *F2CF: 96 8B    ; Load mem to A
        CMPA    #$02                     *F2D1: 81 02    ; Is AccA = 2?
        BNE     ZF29A                    *F2D3: 26 C5    ; If unequal, loop
;
; Resume key processing by managing column mask and counter
ZF2D5   LDD     ColMsk                   *F2D5: DC 8C    ; Load D from mem
        ASLD                             *F2D7: 05       ; Shift D left
        BCS     ZF2DF                    *F2D8: 25 05    ; Branch if carry
        INC     >ColCnt                  *F2DA: 7C 00 8A ; Increase mem
        BRA     ZF2E3                    *F2DD: 20 04    ; Branch to below
ZF2DF   INCB                             *F2DF: 5C       ; Increase AccB
        STAB    ColCnt                   *F2E0: D7 8A    ; Store B there
        INCB                             *F2E2: 5C       ; Increase AccB
ZF2E3   STD     ColMsk                   *F2E3: DD 8C    ; Store D again
        JMP     ZFECC                    *F2E5: 7E FE CC ; Jump far below
;
; Uses 2 lowest bits of AccB as an index for table $MF2F3 to write M008B
ZF2E8   ANDB    #$03                     *F2E8: C4 03    ; Only 2 low bits
        LDX     #MF2F3                   *F2EA: CE F2 F3 ; Base address->X
        ABX                              *F2ED: 3A       ; Add AccB to X
        LDAB    ,X                       *F2EE: E6 00    ; Read mem(X)->B
        STAB    M008B                    *F2F0: D7 8B    ; Store B there
        RTS                              *F2F2: 39       ; Return
MF2F3   FCB     $80                      *F2F3: 80       ; Data ','
        FCB     $01                      *F2F4: 01       ; Data '.'
        FCB     $00                      *F2F5: 00       ; Data '.'
        FCB     $02                      *F2F6: 02       ; Data '.'
;
; This subroutine returns the scancode in AccA of key given in AccA:
; It multiplies ColCnt by 8, adds the detected key (0..7) and looks it up
ZF2F7   LDX     #MF311                   *F2F7: CE F3 11 ; Base address->X
        LDAB    ColCnt                   *F2FA: D6 8A    ; Load mem to B
        CMPB    #$05                     *F2FC: C1 05    ; Check B for $05
        BCS     ZF30D                    *F2FE: 25 0D    ; If lower, branch
        SUBB    #$04                     *F300: C0 04    ; Subtract from B
        ASLB                             *F302: 58       ; Shift left (x2)
        ASLB                             *F303: 58       ; Shift left (x4)
        ASLB                             *F304: 58       ; Shift left (x8)
        ABX                              *F305: 3A       ; Add AccB to X
        CLRB                             *F306: 5F       ; Clear AccB
        BRA     ZF30A                    *F307: 20 01    ; Skip next only
ZF309   INCB                             *F309: 5C       ; Increase AccB
ZF30A   LSRA                             *F30A: 44       ; Shift AccA right
        BCC     ZF309                    *F30B: 24 FC    ; Loop if no carry
ZF30D   ABX                              *F30D: 3A       ; Add AccB to X
        LDAA    ,X                       *F30E: A6 00    ; Load mem(X)->A
        RTS                              *F310: 39       ; Return
MF311   FCB     $00                      *F311: 00       ; Unused, Col 5
        FCB     $00                      *F312: 00       ; Unused
        FCB     $3B                      *F313: 3B       ; 'F1'
        FCB     $3C                      *F314: 3C       ; 'F2'
        FCB     $3D                      *F315: 3D       ; 'F3'
        FCB     $00                      *F316: 00       ; Unused
        FCB     $00                      *F317: 00       ; Unused
        FCB     $00                      *F318: 00       ; Unused
        FCB     $3E                      *F319: 3E       ; 'F4', Col 6
        FCB     $01                      *F31A: 01       ; 'Esc'
        FCB     $02                      *F31B: 02       ; '1'
        FCB     $0F                      *F31C: 0F       ; 'Tab'
        FCB     $10                      *F31D: 10       ; 'Q'
        FCB     $1E                      *F31E: 1E       ; 'A'
        FCB     $60                      *F31F: 60       ; 'Iso Key'
        FCB     $2C                      *F320: 2C       ; 'Z'
        FCB     $3F                      *F321: 3F       ; 'F5', Col 7
        FCB     $03                      *F322: 03       ; '2'
        FCB     $04                      *F323: 04       ; '3'
        FCB     $11                      *F324: 11       ; 'W'
        FCB     $12                      *F325: 12       ; 'E'
        FCB     $1F                      *F326: 1F       ; 'S'
        FCB     $20                      *F327: 20       ; 'D'
        FCB     $2D                      *F328: 2D       ; 'X'
        FCB     $40                      *F329: 40       ; 'F6', Col 8
        FCB     $05                      *F32A: 05       ; '4'
        FCB     $06                      *F32B: 06       ; '5'
        FCB     $13                      *F32C: 13       ; 'R'
        FCB     $14                      *F32D: 14       ; 'T'
        FCB     $21                      *F32E: 21       ; 'F'
        FCB     $2E                      *F3EF; 2E       ; 'C'
        FCB     $2F                      *F330: 2F       ; 'V'
        FCB     $41                      *F331: 41       ; 'F7', Col 9
        FCB     $07                      *F332: 07       ; '6'
        FCB     $08                      *F333: 08       ; '7'
        FCB     $15                      *F334: 15       ; 'Y'
        FCB     $22                      *F335: 22       ; 'G'
        FCB     $23                      *F337: 23       ; 'H'
        FCB     $30                      *F337: 30       ; 'B'
        FCB     $31                      *F338: 31       ; 'N'
        FCB     $42                      *F339: 42       ; 'F8', Col 10
        FCB     $09                      *F33A: 09       ; '8'
        FCB     $0A                      *F33B: 0A       ; '9'
        FCB     $16                      *F33C: 16       ; 'U'
        FCB     $17                      *F33D: 17       ; 'I'
        FCB     $24                      *F33E: 24       ; 'J'
        FCB     $25                      *F33F: 25       ; 'K'
        FCB     $32                      *F340: 32       ; 'M'
        FCB     $43                      *F341: 43       ; 'F9', Col 11
        FCB     $0B                      *F342: 0B       ; '0'
        FCB     $0C                      *F343: 0C       ; '-'
        FCB     $18                      *F344: 18       ; 'O'
        FCB     $19                      *F345: 19       ; 'P'
        FCB     $26                      *F346: 26       ; 'L'
        FCB     $33                      *F347: 33       ; ','
        FCB     $39                      *F348: 39       ; ' '
        FCB     $44                      *F349: 44       ; 'F10'', Col 12
        FCB     $0D                      *F34A: 0D       ; '='
        FCB     $29                      *F34B: 29       ; '`'
        FCB     $1A                      *F34C: 1A       ; '['
        FCB     $1B                      *F34D: 1B       ; ']'
        FCB     $27                      *F34E: 27       ; ';'
        FCB     $34                      *F34F: 34       ; '.'
        FCB     $3A                      *F350: 3A       ; 'CapsLock'
        FCB     $62                      *F351: 62       ; 'Help', Col 13
        FCB     $0E                      *F352: 0E       ; 'Backspace'
        FCB     $53                      *F253: 53       ; 'Delete'
        FCB     $52                      *F354: 52       ; 'Insert'
        FCB     $2B                      *F355: 2B       ; '\'
        FCB     $1C                      *F356: 1C       ; 'Return'
        FCB     $28                      *F357: 28       ; '''
        FCB     $35                      *F358: 35       ; '/'
        FCB     $61                      *F359: 61       ; 'Undo', Col 14
        FCB     $48                      *F35A: 48       ; 'Up'
        FCB     $47                      *F35B: 47       ; 'Clr/Home'
        FCB     $4B                      *F35C: 4B       ; 'Left'
        FCB     $50                      *F35D: 50       ; 'Down'
        FCB     $4D                      *F35E: 4D       ; 'Right'
        FCB     $6D                      *F35F: 6D       ; Keypad '1'
        FCB     $70                      *F360: 70       ; Keypad '0'
        FCB     $63                      *F361: 63       ; Keypad '(',Col15
        FCB     $64                      *F362: 64       ; Keypad ')'
        FCB     $67                      *F363: 67       ; Keypad '7'
        FCB     $68                      *F364: 68       ; Keypad '8'
        FCB     $6A                      *F365: 6A       ; Keypad '4'
        FCB     $6B                      *F366: 6B       ; Keypad '5'
        FCB     $6E                      *F367: 6E       ; Keypad '2'
        FCB     $71                      *F368: 71       ; Keypad '.'
        FCB     $65                      *F369: 65       ; Keypad '/',Col16
        FCB     $66                      *F36A: 66       ; Keypad '*'
        FCB     $69                      *F36B: 69       ; Keypad '9'
        FCB     $4A                      *F36C: 4A       ; Keypad '-'
        FCB     $6C                      *F36D: 6C       ; Keypad '6'
        FCB     $4E                      *F36E: 4E       ; Keypad '+'
        FCB     $6F                      *F36F: 6F       ; Keypad '3'
        FCB     $72                      *F370: 72       ; Keypad 'Enter'
;
; Main function continues here, AccA contains P4DAT, i.e. 74LS244 latch
ZF371   ANDA    #$0F                     *F371: 84 0F    ; Low Nibble of A
        STAA    M00C6                    *F373: 97 C6    ; Store A there
        ANDA    #$03                     *F375: 84 03    ; Low 2 bits of A
        LDX     #MXraw                   *F377: CE 00 BE ; Base address->X
        CLR     >MAccLo                  *F37A: 7F 00 C8 ; Clear mem
        LDAB    M00C3                    *F37D: D6 C3    ; Load mem to B
        JSR     ZF3E3                    *F37F: BD F3 E3 ; Subroutine
        STAA    M00C3                    *F382: 97 C3    ; Store A there
        LDAA    M00C6                    *F384: 96 C6    ; Load mem to A
        LSRA                             *F386: 44       ; Shift A right
        LSRA                             *F387: 44       ; Shift A right
        ANDA    #$03                     *F388: 84 03    ; Low 2 bits of A
        LDX     #MYraw                   *F38A: CE 00 BF ; Base address->X
        LDAB    #$01                     *F38D: C6 01    ; Set AccB to 1
        STAB    MAccLo                   *F38F: D7 C8    ; Store B there
        LDAB    M00C4                    *F391: D6 C4    ; Load B from mem
        JSR     ZF3E3                    *F393: BD F3 E3 ; Subroutine
        STAA    M00C4                    *F396: 97 C4    ; Store A there
        CLR     >MBStat                  *F398: 7F 00 C1 ; Clear mem
        LDAB    MBfP2                    *F39B: D6 9B    ; Load B from mem
        ANDB    #$06                     *F39D: C4 06    ; Bits 1+2 of B
        BEQ     ZF3A5                    *F39F: 27 04    ; If zero skip...
        CMPB    #$06                     *F3A1: C1 06    ; ...comparing
        BNE     ZF3A7                    *F3A3: 26 02    ; Skip if not eq.
ZF3A5   EORB    #$06                     *F3A5: C8 06    ; XOR B with 6
ZF3A7   TBA                              *F3A7: 17       ; Transfer B->A
        EORB    MBraw                    *F3A8: D8 C0    ; XOR B with mem
        BEQ     ZF3CB                    *F3AA: 27 1F    ; If zero, branch
        STAA    MBraw                    *F3AC: 97 C0    ; Store A there
        STAB    M00C5                    *F3AE: D7 C5    ; Store B there
        TAB                              *F3B0: 16       ; Transfer A->B
        ANDB    M00C5                    *F3B1: D4 C5    ; AND B with mem
        STAB    M00C6                    *F3B3: D7 C6    ; Store B there
        LSRB                             *F3B5: 54       ; Shift B right
        ORAB    M00C6                    *F3B6: DA C6    ; OR B with mem
        ANDB    #$05                     *F3B8: C4 05    ; AND B with 5
        STAB    MBStat                   *F3BA: D7 C1    ; Store B there
        COMA                             *F3BC: 43       ; Invert AccA
        TAB                              *F3BD: 16       ; Transfer A->B
        ANDB    M00C5                    *F3BE: D4 C5    ; AND B with mem
        STAB    M00C6                    *F3C0: D7 C6    ; Store B there
        ASLB                             *F3C2: 58       ; Shift B left
        ORAB    M00C6                    *F3C3: DA C6    ; OR B with mem
        ANDB    #$0A                     *F3C5: C4 0A    ; AND B with $0A
        ORAB    MBStat                   *F3C7: DA C1    ; OR B with mem
        STAB    MBStat                   *F3C9: D7 C1    ; Store B there
ZF3CB   LDAA    MMode                    *F3CB: 96 C9    ; Load mem to A
        ASLA                             *F3CD: 48       ; Shift A left
        ASLA                             *F3CE: 48       ; Shift A left
        BCC     ZF3D4                    *F3CF: 24 03    ; Skip if no carry
        JMP     ZF5EB                    *F3D1: 7E F5 EB ; Jump to below
ZF3D4   ASLA                             *F3D4: 48       ; Shift A left
        BCC     ZF3DA                    *F3D5: 24 03    ; Skip if no carry
        JMP     ZF439                    *F3D7: 7E F4 39 ; Jump to below
ZF3DA   ASLA                             *F3DA: 48       ; Shift A left
        BCC     ZF3E0                    *F3DB: 24 03    ; Skip if no carry
        JMP     ZF4BA                    *F3DD: 7E F4 BA ; Jump to below
ZF3E0   JMP     ZF150                    *F3E0: 7E F1 50 ; Jump back up
;
; Subroutine
;  AccA = Raw mouse pin data (Bit 0=MXb or MYa, Bit1=MXa or MYb) from P4
;  AccB = Presumed mouse X or Y configuration
;     X = Mouse raw coordinate pointer (X or Y)
;  Returns updated mouse X or Y configuration in AccB
ZF3E3   ANDB    #$E0                     *F3E3: C4 E0    ; Top 3 bits of B
        STAA    M00C5                    *F3E5: 97 C5    ; Store A there
        EORA    ,X                       *F3E7: A8 00    ; XOR with mem(X)
        BEQ     ZF434                    *F3E9: 27 49    ; If zero, branch
        CMPA    #$03                     *F3EB: 81 03    ; Compare A=3?
        BNE     ZF3F4                    *F3ED: 26 05    ; If not, branch
        ORAB    #$02                     *F3EF: CA 02    ; OR B with $02
        TBA                              *F3F1: 17       ; Transfer B->A
        BRA     ZF42F                    *F3F2: 20 3B    ; Branch to below
ZF3F4   PSHB                             *F3F4: 37       ; Push B to stack
        LDAB    ,X                       *F3F5: E6 00    ; Load mem(X)->B
        BEQ     ZF400                    *F3F7: 27 07    ; If zero, branch
        CMPB    #$03                     *F3F9: C1 03    ; Compare B=3?
        BEQ     ZF400                    *F3FB: 27 03    ; If equal, skip
        COMA                             *F3FD: 43       ; Invert AccA
        ANDA    #$03                     *F3FE: 84 03    ; Only 2 low bits
ZF400   PULB                             *F400: 33       ; Get B from stack
        CMPA    #$01                     *F401: 81 01    ; Compare A=1?
        BNE     ZF413                    *F403: 26 0E    ; If not, branch
        BITB    #$60                     *F405: C5 60    ; Test B, bits 1+2
        BEQ     ZF41F                    *F407: 27 16    ; Branch if clear
        LDAA    #$01                     *F409: 86 01    ; Load 1 to AccA
        SUBB    #$20                     *F40B: C0 20    ; Sub $20 from B
        BITB    #$60                     *F40D: C5 60    ; Test B, bits 1+2
        BEQ     ZF41F                    *F40F: 27 0E    ; If zero, branch
        BRA     ZF436                    *F411: 20 23    ; Branch to below
ZF413   BITB    #$40                     *F413: C5 40    ; Test B, bit 2
        BNE     ZF41D                    *F415: 26 06    ; If set, branch
        ADDB    #$20                     *F417: CB 20    ; Add $20 to B
        BITB    #$40                     *F419: C5 40    ; Test B, Bit 2
        BEQ     ZF436                    *F41B: 27 19    ; Branch if zero
ZF41D   LDAA    #$C1                     *F41D: 86 C1    ; Set AccA to $C1
ZF41F   LDAB    MAccLo                   *F41F: D6 C8    ; Load mem to AccB
        BEQ     ZF42D                    *F421: 27 0A    ; If not 0, branch
        TIM     #$40,MMode               *F423: 7B 40 C9 ; Test mem bit 6
        BNE     ZF42F                    *F426: 26 07    ; If set, branch
        TIM     #$01,MMode               *F428: 7B 01 C9 ; Test mem bit 0
        BNE     ZF42F                    *F42B: 26 02    ; if set, skip...
ZF42D   EORA    #$80                     *F42D: 88 80    ; ...XOR A bit 7
ZF42F   LDAB    M00C5                    *F42F: D6 C5    ; Load mem to AccB
        STAB    ,X                       *F431: E7 00    ; Store B->(mem)X
        RTS                              *F433: 39       ; Return
ZF434   TBA                              *F434: 17       ; Transfer B->A
        RTS                              *F435: 39       ; Return
ZF436   TBA                              *F436: 17       ; Transfer B->A
        BRA     ZF42F                    *F437: 20 F6    ; Branch to above
;
ZF439   LDX     #MYCoord                 *F439: CE 00 B8 ; Base address->X
        LDD     MAbMaxY                  *F43C: DC AC    ; Read mem to D
        STD     M00C5                    *F43E: DD C5    ; Store D there
        LDAA    MAbsScY                  *F440: 96 B3    ; Load mem to AccA
        LDAB    M00C4                    *F442: D6 C4    ; Load mem to AccB
        JSR     ZF488                    *F444: BD F4 88 ; Subroutine
        LDX     #MXCoord                 *F447: CE 00 B6 ; Base address->X
        LDD     MAbMaxX                  *F44A: DC AA    ; Load mem to D
        STD     M00C5                    *F44C: DD C5    ; Store D there
        LDAA    MAbsScX                  *F44E: 96 B2    ; Load mem to AccA
        LDAB    M00C3                    *F450: D6 C3    ; Load mem to AccB
        JSR     ZF488                    *F452: BD F4 88 ; Subroútine
        LDAB    MBStat                   *F455: D6 C1    ; Load mem to AccB
        BEQ     ZF485                    *F457: 27 2C    ; If zero, branch
        TBA                              *F459: 17       ; Transfer B->A
        ORAA    M00C2                    *F45A: 9A C2    ; OR AccA with mem
        STAA    M00C2                    *F45C: 97 C2    ; Store AccA there
        TIM     #$04,MBActn              *F45E: 7B 04 B4 ; Test mem bit 2
        BEQ     ZF466                    *F461: 27 03    ; If clear, branch
        JMP     ZF62B                    *F463: 7E F6 2B ; If not, jump
ZF466   CLRA                             *F466: 4F       ; Clear AccA
        BITB    #$05                     *F467: C5 05    ; Test B bits 0,2
        BEQ     ZF46D                    *F469: 27 02    ; Branch if both 0
        ORAA    #$01                     *F46B: 8A 01    ; Set Bit 0 in A
ZF46D   BITB    #$0A                     *F46D: C5 0A    ; Test B bits 1,3
        BEQ     ZF473                    *F46F: 27 02    ; Branch if both 0
        ORAA    #$02                     *F471: 8A 02    ; Set Bit 1 in A
ZF473   ANDA    MBActn                   *F473: 94 B4    ; AND A with mem
        BEQ     ZF485                    *F475: 27 0E    ; If zero, branch
        STAB    MBEvnt                   *F477: D7 B5    ; Store B there
        LDAB    #$05                     *F479: C6 05    ; Set B to $05
        LDX     #MBEvnt                  *F47B: CE 00 B5 ; Base address->X
        SEI                              *F47E: 0F       ; Disable IRQs
        LDAA    #$F7                     *F47F: 86 F7    ; Load $F7 to AccA
        JSR     ZFD34                    *F481: BD FD 34 ; Subroutine
        CLI                              *F484: 0E       ; Enable IRQs
ZF485   JMP     ZF150                    *F485: 7E F1 50 ; Jump to above
;
; Subroutine to calculate mouse X or Y coordinates
;   AccB = Configuration bitfield
;   AccA = Mouse absolute scaling
;      X = Mouse coordinate pointer (X or Y)
ZF488   BITB    #$03                     *F488: C5 03    ; Test B bits 0,1
        BEQ     ZF4B9                    *F48A: 27 2D    ; All 0? Branch.
ZF48C   PSHB                             *F48C: 37       ; Push B to Stack
        ASLB                             *F48D: 58       : Shift B left
        TAB                              *F48E: 16       ; Transfer A->B
        LDAA    #$00                     *F48F: 86 00    ; Load $00 to AccA
        STD     MAccHi                   *F491: DD C7    ; Store A+B in mem
        LDD     ,X                       *F493: EC 00    ; Load (mem)X to D
        BCC     ZF4A0                    *F495: 24 09    ; Carry=0? Branch
        SUBD    MAccHi                   *F497: 93 C7    ; Sub. mem from D
        BCC     ZF4A2                    *F499: 24 07    ; Carry=0? Branch
        LDD     #$0000                   *F49B: CC 00 00 ; Reset D to 0
        BRA     ZF4B6                    *F49E: 20 16    ; Branch ahead
ZF4A0   ADDD    MAccHi                   *F4A0: D3 C7    ; Add mem to D
ZF4A2   STD     MAccHi                   *F4A2: DD C7    ; Store D there
        SUBD    M00C5                    *F4A4: 93 C5    ; Sub. mem from D
        BCC     ZF4B4                    *F4A6: 24 0C    ; No carry? Branch
        LDD     MAccHi                   *F4A8: DC C7    ; Load mem to D
        STD     ,X                       *F4AA: ED 00    ; Store D->mem(X)
        PULB                             *F4AC: 33       ; Get B from stack
        SUBB    #$01                     *F4AD: C0 01    ; Decrease B by 1
        BITB    #$01                     *F4AF: C5 01    ; Test B bit 0
        BNE     ZF48C                    *F4B1: 26 D9    ; If set, branch
        RTS                              *F4B3: 39       ; Return
ZF4B4   LDD     M00C5                    *F4B4: DC C5    ; Read mem to D
ZF4B6   STD     ,X                       *F4B6: ED 00    ; Store D->mem(X)
        PULB                             *F4B8: 33       ; Get B from stack
ZF4B9   RTS                              *F4B9: 39       ; Return
;
ZF4BA   CLR     >M00C6                   *F4BA: 7F 00 C6 ; Clear mem.byte
        LDAB    M00C4                    *F4BD: D6 C4    ; Load mem to B
        STAB    MAccLo                   *F4BF: D7 C8    ; Store B there
        AIM     #$03,MAccLo              *F4C1: 71 03 C8 ; AND mem with $03
        LDAA    MRelDy                   *F4C4: 96 BD    ; Load mem to AccA
        ASLB                             *F4C6: 58       ; Shift B left
        BCC     ZF4EE                    *F4C7: 24 25    ; If no carry, go
        SUBA    MAccLo                   *F4C9: 90 C8    ; Sub. mem from A
        CMPA    #$81                     *F4CB: 81 81    ; Check ~max.neg.
        BCC     ZF4D7                    *F4CD: 24 08    ; Branch if lower
        CMPA    #$7F                     *F4CF: 81 7F    ; Check max.pos.
        BCS     ZF4D7                    *F4D1: 25 04    ; Branch if higher
        LDAA    #$80                     *F4D3: 86 80    ; Set to max.neg.
        STAA    M00C6                    *F4D5: 97 C6    ; Store there
ZF4D7   STAA    MRelDy                   *F4D7: 97 BD    ; Also, store here
        BPL     ZF4E5                    *F4D9: 2A 0A    ; Branch if pos.
        NEGA                             *F4DB: 40       ; Change sign
        CMPA    MEvThrY                  *F4DC: 91 B1    ; Compare mem to A
        BCS     ZF4FF                    *F4DE: 25 1F    ; Branch if lower
        OIM     #$02,M00C6               *F4E0: 72 02 C6 ; OR mem. with $02
        BRA     ZF4FF                    *F4E3: 20 1A    ; Branch to below
ZF4E5   CMPA    MEvThrY                  *F4E5: 91 B1    ; Compre mem to A
        BCS     ZF4FF                    *F4E7: 25 16    ; Branch if lower
        OIM     #$01,M00C6               *F4E9: 72 01 C6 ; OR mem with $01
        BRA     ZF4FF                    *F4EC: 20 11    ; Branch to below
ZF4EE   ADDA    MAccLo                   *F4EE: 9B C8    ; Add mem to AccA
        CMPA    #$7F                     *F4F0: 81 7F    ; Check max.pos.
        BCS     ZF4D7                    *F4F2: 25 E3    ; Branch if lower
        CMPA    #$81                     *F4F4: 81 81    ; Check ~max.neg.
        BCC     ZF4D7                    *F4F6: 24 DF    ; Branch if higher
        OIM     #$40,M00C6               *F4F8: 72 40 C6 ; OR mem with $40
        LDAA    #$7F                     *F4FB: 86 7F    ; Set to max.pos.
        BRA     ZF4D7                    *F4FD: 20 D8    ; Loop
ZF4FF   LDAB    M00C3                    *F4FF: D6 C3    ; Load mem to AccB
        STAB    MAccLo                   *F501: D7 C8    ; Store B there
        AIM     #$03,MAccLo              *F503: 71 03 C8 ; AND mem with $03
        LDAA    MRelDx                   *F506: 96 BC    ; Load mem to AccA
        ASLB                             *F508: 58       ; Shift B left
        BCC     ZF531                    *F509: 24 26    ; No carry? Branch
        SUBA    MAccLo                   *F50B: 90 C8    ; Sub. mem from A
        CMPA    #$81                     *F50D: 81 81    ; Check ~max.neg.
        BCC     ZF51A                    *F50F: 24 09    ; Branch if higher
        CMPA    #$7F                     *F511: 81 7F    ; Check max.pos.
        BCS     ZF51A                    *F513: 25 05    ; Branch if lower
        LDAA    #$80                     *F515: 86 80    ; Set A to max.neg
        OIM     #$80,M00C6               *F517: 72 80 C6 ; OR mem with $80
ZF51A   STAA    MRelDx                   *F51A: 97 BC    ; Store A there
        BPL     ZF528                    *F51C: 2A 0A    ; If pos., branch
        NEGA                             *F51E: 40       ; Otherwise,negate
        CMPA    MEvThrX                  *F51F: 91 B0    ; Comp. A with mem
        BCS     ZF542                    *F521: 25 1F    ; Branch if lower
        OIM     #$02,M00C6               *F523: 72 02 C6 ; OR mem with $02
        BRA     ZF542                    *F526: 20 1A    ; Branch to below
ZF528   CMPA    MEvThrX                  *F528: 91 B0    ; Comp. A with mem
        BCS     ZF542                    *F52A: 25 16    ; Branch if lower
        OIM     #$01,M00C6               *F52C: 72 01 C6 ; OR mem with $01
        BRA     ZF542                    *F52F: 20 11    ; Branch to below
ZF531   ADDA    MAccLo                   *F531: 9B C8    ; Add mem to AccA
        CMPA    #$7F                     *F533: 81 7F    ; Check max.pos.
        BCS     ZF51A                    *F535: 25 E3    ; Branch if lower
        CMPA    #$81                     *F537: 81 81    ; Check ~max.neg.
        BCC     ZF51A                    *F539: 24 DF    ; Branch if higher
        OIM     #$40,M00C6               *F53B: 72 40 C6 ; OR mem with $40
        LDAA    #$7F                     *F53E: 86 7F    ; Set A to max.pos
        BRA     ZF51A                    *F540: 20 D8    ; Branch to below
ZF542   LDAA    M00C6                    *F542: 96 C6    ; Load mem to AccA
        BEQ     ZF55B                    *F544: 27 15    ; If zero, branch
        ANDA    #$C0                     *F546: 84 C0    ; Top 2 Bits of A
        BNE     ZF581                    *F548: 26 37    ; If not 0, branch
        TIM     #$08,MMode               *F54A: 7B 08 C9 ; Test mem bit 3
        BNE     ZF556                    *F54D: 26 07    ; if set, branch
        TIM     #$0F,MBStat              *F54F: 7B 0F C1 ; Test mem for $0F
        BEQ     ZF5A5                    *F552: 27 51    ; If zero, branch
        BRA     ZF581                    *F554: 20 2B    ; Branch to below
ZF556   TIM     #$80,M00D7               *F556: 7B 80 D7 ; Test mem bit 7
        BNE     ZF581                    *F559: 26 26    ; If set, branch
ZF55B   TIM     #$0F,MBStat              *F55B: 7B 0F C1 ; Test mem for $0F
        BEQ     ZF5A5                    *F55E: 27 45    ; If all 0, branch
        TIM     #$04,MBActn              *F560: 7B 04 B4 ; Test mem bit 2
        BEQ     ZF568                    *F563: 27 03    ; If clear, branch
        JMP     ZF62B                    *F565: 7E F6 2B ; Jump to below
;
; Report relative mouse coordinates plus mouse buttons with $F8..$FB
ZF568   LDAA    MBraw                    *F568: 96 C0    ; Load mem to AccA
        LSRA                             *F56A: 44       ; Shift A right
        ORAA    #$F8                     *F56B: 8A F8    ; Set top 5 bits
        LDX     #MRelDx                  *F56D: CE 00 BC ; Base address->X
        SEI                              *F570: 0F       ; Disable IRQs
        LDAB    #$02                     *F571: C6 02    ; Load $02 to B
        JSR     ZFD34                    *F573: BD FD 34 ; Subroutine
        BCC     ZF57E                    *F576: 24 06    ; No carry? Branch
        CLR     >MRelDy                  *F578: 7F 00 BD ; Clear mem byte
        CLR     >MRelDx                  *F57B: 7F 00 BC ; Clear mem byte
ZF57E   CLI                              *F57E: 0E       ; Enable IRQs
        BRA     ZF5A5                    *F57F: 20 24    ; Branch to below
ZF581   LDAA    MBraw                    *F581: 96 C0    ; Load mem to AccA
        LSRA                             *F583: 44       ; Shift A right
        ORAA    #$F8                     *F584: 8A F8    ; Set top 5 bits
        LDX     #MRelDx                  *F586: CE 00 BC ; Base address->X
        SEI                              *F589: 0F       ; Disable IRQs
        LDAB    #$02                     *F58A: C6 02    ; Set AccB to $02
        JSR     ZFD34                    *F58C: BD FD 34 ; Subroutine
        BCC     ZF597                    *F58F: 24 06    ; No carry? Branch
        CLR     >MRelDy                  *F591: 7F 00 BD ; Clear mem byte
        CLR     >MRelDx                  *F594: 7F 00 BC ; Clear mem byte
ZF597   CLI                              *F597: 0E       ; Enable IRQs
        TIM     #$0F,MBStat              *F598: 7B 0F C1 ; Test mem for $0F
        BEQ     ZF5A5                    *F59B: 27 08    ; If all 0, branch
        TIM     #$04,MBActn              *F59D: 7B 04 B4 ; Test mem bit 2
        BEQ     ZF5A5                    *F5A0: 27 03    ; If clear, branch
        JMP     ZF62B                    *F5A2: 7E F6 2B ; Jump to below
ZF5A5   JMP     ZF150                    *F5A5: 7E F1 50 ; Jump far up
;
; Subroutine to add Delta mouse movement and check for overflow/underflow
;   AccB: Configuration bitfield (Bit 0: Whether to add/subtract)
;      X: Pointer to current mouse coordinates
;   Overwrites M00C6
ZF5A8   CLR     >M00C6                   *F5A8: 7F 00 C6 ; Clear mem byte
        STAB    MAccLo                   *F5AB: D7 C8    ; Store B there
        AIM     #$03,MAccLo              *F5AD: 71 03 C8 ; AND mem with $03
        LDAA    ,X                       *F5B0: A6 00    ; Load (mem)X to A
        ASLB                             *F5B2: 58       ; Shift B left
        BCC     ZF5DA                    *F5B3: 24 25    ; No carry? Branch
        SUBA    MAccLo                   *F5B5: 90 C8    ; Sub. mem from A
        CMPA    #$81                     *F5B7: 81 81    ; Check ~max.neg.
        BCC     ZF5C4                    *F5B9: 24 09    ; Branch if higher
        CMPA    #$7F                     *F5BB: 81 7F    ; Check max.pos.
        BCS     ZF5C4                    *F5BD: 25 05    ; If lower, branch
        OIM     #$80,M00C6               *F5BF: 72 80 C6 ; OR mem with $80
        LDAA    #$80                     *F5C2: 86 80    ; Set AccA to $80
ZF5C4   STAA    ,X                       *F5C4: A7 00    ; Write A->mem(X)
        BPL     ZF5D2                    *F5C6: 2A 0A    ; If pos. branch
        NEGA                             *F5C8: 40       ; Negate AccA
        CMPA    M00C5                    *F5C9: 91 C5    ; Check A with mem
        BCS     ZF5D9                    *F5CB: 25 0C    ; If lower, branch
        OIM     #$02,M00C6               *F5CD: 72 02 C6 ; OR mem with $02
        BRA     ZF5D9                    *F5D0: 20 07    ; Branch to below
ZF5D2   CMPA    M00C5                    *F5D2: 91 C5    ; Check A with mem
        BCS     ZF5D9                    *F5D4: 25 03    ; If lower, branch
        OIM     #$01,M00C6               *F5D6: 72 01 C6 ; OR mem with $01
ZF5D9   RTS                              *F5D9: 39       ; Return
ZF5DA   ADDA    MAccLo                   *F5DA: 9B C8    ; Add mem to AccA
        CMPA    #$7F                     *F5DC: 81 7F    ; Check max.pos.
        BCS     ZF5C4                    *F5DE: 25 E4    ; If lower, branch
        CMPA    #$81                     *F5E0: 81 81    ; Check ~max.neg.
        BCC     ZF5C4                    *F5E2: 24 E0    ; Branch if higher
        OIM     #$40,M00C6               *F5E4: 72 40 C6 ; OR mem with $40
        LDAA    #$7F                     *F5E7: 86 7F    ; Max.Pos. to AccA
        BRA     ZF5C4                    *F5E9: 20 D9    ; Branch to above
;
ZF5EB   LDAA    M00AF                    *F5EB: 96 AF    ; Load mem to AccA
        STAA    M00C5                    *F5ED: 97 C5    ; Store A there
        LDX     #M00BB                   *F5EF: CE 00 BB ; Base address->X
        LDAB    M00C4                    *F5F2: D6 C4    ; Load mem to AccB
        JSR     ZF5A8                    *F5F4: BD F5 A8 ; Subroutine
        LDAA    M00C6                    *F5F7: 96 C6    ; Load mem to AccA
        BEQ     ZF60B                    *F5F9: 27 10    ; If zero, branch
        ANDA    #$82                     *F5FB: 84 82    ; Bits 7,1 of AccA
        BEQ     ZF603                    *F5FD: 27 04    ; All Zero? Branch
        LDAB    #$01                     *F5FF: C6 01    ; Set AccB to $01
        BRA     ZF605                    *F601: 20 02    ; Skip next instr.
ZF603   LDAB    #$00                     *F603: C6 00    ; Set AccB to $00
ZF605   JSR     ZF656                    *F605: BD F6 56 ; Subroutine
        CLR     >M00BB                   *F608: 7F 00 BB ; Clear mem byte
ZF60B   LDAA    MKCodDx                  *F60B: 96 AE    ; Load mem to AccA
        STAA    M00C5                    *F60D: 97 C5    ; Store A there
        LDX     #M00BA                   *F60F: CE 00 BA ; Base Address->X
        LDAB    M00C3                    *F612: D6 C3    ; Load mem to AccB
        JSR     ZF5A8                    *F614: BD F5 A8 ; Subroutine
        LDAA    M00C6                    *F617: 96 C6    ; Load mem to AccA
        BEQ     ZF62B                    *F619: 27 10    ; If zero, branch
        ANDA    #$82                     *F61B: 84 82    ; Mask A bits 7,1
        BEQ     ZF623                    *F61D: 27 04    ; All zero? Branch
        LDAB    #$03                     *F61F: C6 03    ; Load $03 to AccB
        BRA     ZF625                    *F621: 20 02    ; Skip next instr.
ZF623   LDAB    #$02                     *F623: C6 02    ; Load $02 to AccB
ZF625   JSR     ZF656                    *F625: BD F6 56 ; Subroutine
        CLR     >M00BA                   *F628: 7F 00 BA ; Clear mem byte
;
; Decide for make/break code for the right mouse button
ZF62B   LDAB    MBStat                   *F62B: D6 C1    ; Load mem to AccB
        BEQ     ZF653                    *F62D: 27 24    ; If zero, branch
        ANDB    #$03                     *F62F: C4 03    ; Mask B bits 1,0
        BEQ     ZF63F                    *F631: 27 0C    ; All zero? Branch
        LSRB                             *F633: 54       ; Shift B right
        BCC     ZF63A                    *F634: 24 04    ; No carry? Branch
        LDAB    #$05                     *F636: C6 05    ; Load $05 to AccB
        BRA     ZF63C                    *F638: 20 02    ; Skip next instr.
ZF63A   LDAB    #$07                     *F63A: C6 07    ; Load $07 to AccB
ZF63C   JSR     ZF656                    *F63C: BD F6 56 ; Subroutine
;
; Decide for make/break code for the left mouse button
ZF63F   LDAB    MBStat                   *F63F: D6 C1    ; Load mem to AccB
        ANDB    #$0C                     *F641: C4 0C    ; Mask Bits 3,2
        BEQ     ZF653                    *F643: 27 0E    ; All zero? Branch
        LSRB                             *F645: 54       ; Shift B right
        LSRB                             *F646: 54       ; Shift B right
        LSRB                             *F647: 54       ; Shift B right
        BCC     ZF64E                    *F648: 24 04    ; No carry? Branch
        LDAB    #$04                     *F64A: C6 04    ; Load $04 to AccB
        BRA     ZF650                    *F64C: 20 02    ; Skip next instr.
ZF64E   LDAB    #$06                     *F64E: C6 06    ; Load $06 to AccB
ZF650   JSR     ZF656                    *F650: BD F6 56 ; Subroutine
ZF653   JMP     ZF150                    *F653: 7E F1 50 ; Jump to above
;
; Subroutine to look up and transmit make/break codes of Cursor and Buttons
;   AccB = Offset for the lookup table at MF679
;   Clears MAccHi. If AccB < 4, two responses (make+break) are sent
ZF656   CLR     >MAccHi                  *F656: 7F 00 C7 ; Clear mem byte
        LDX     #MF679                   *F659: CE F6 79 ; Base address->X
        ABX                              *F65C: 3A       ; Add AccB to X
        LDAA    ,X                       *F65D: A6 00    ; Fetch mem(X)->A
        CMPA    #$60                     *F65F: 81 60    ; Is it $60?
        BCC     ZF665                    *F661: 24 02    ; Branch if higher
        STAA    MAccHi                   *F663: 97 C7    ; Store A there
ZF665   SEI                              *F665: 0F       ; Disable IRQs
        CLRB                             *F666: 5F       ; Clear AccB
        JSR     ZFD34                    *F667: BD FD 34 ; Subroutine
        BCC     ZF677                    *F66A: 24 0B    ; No carry? Branch
        LDAA    MAccHi                   *F66C: 96 C7    ; Load mem to AccA
        BEQ     ZF677                    *F66E: 27 07    ; If zero, branch
        ORAA    #$80                     *F670: 8A 80    ; Set Bit 7 of A
        CLR     >MAccHi                  *F672: 7F 00 C7 ; Clear mem byte
        BRA     ZF665                    *F675: 20 EE    ; Loop
ZF677   CLI                              *F677: 0E       ; Enable IRQs
        RTS                              *F678: 39       ; Return
;
; For joystick keycode mode, this table features make codes for the
; cursor equivalents and make/break codes for the fire buttons
MF679   FCB     $48                      *F679: 48       ; Cursor Up
        FCB     $50                      *F67A: 50       ; Cursor Down
        FCB     $4D                      *F67B: 4D       ; Cursor Left
        FCB     $4B                      *F67C: 4B       ; Cursor Right
        FCB     $74                      *F67D: 74       ; J0 Button make
        FCB     $75                      *F67E: 75       ; J1 Button make
        FCB     $F4                      *F67F: F4       ; J0 Button break
        FCB     $F5                      *F680: F5       ; J1 Button break
;
ZF681   COMA                             *F681: 43       ; Invert AccA
        LDAB    M009E                    *F682: D6 9E    ; Load mem to AccB
        BEQ     ZF68D                    *F684: 27 15    ; If zero, branch
        CMPB    #$05                     *F686: C1 05    ; Check for $05
        BCS     ZF6A4                    *F688: 25 1A    ; If lower, branch
        CLRB                             *F68A: 5F       ; Clear AccB
        STAB    M009E                    *F68B: D7 9E    ; Store B there
ZF68D   STAA    M00C5                    *F68D: 97 C5    ; Store A here
        TAB                              *F68F: 16       ; Transfer A->B
        EORA    M00A0                    *F690: 98 A0    ; EOR A with mem
        ANDA    M009F                    *F692: 94 9F    ; AND A with mem
        ANDB    M00A0                    *F694: D4 A0    ; AND B with mem
        ABA                              *F696: 1B       ; Add AccB to AccA
        STAA    M009F                    *F697: 97 9F    ; Store A here
        LDAA    M00C5                    *F699: 96 C5    ; Read mem to AccA
        CMPA    M009F                    *F69B: 91 9F    ; Compare A to mem
        BEQ     ZF6A4                    *F69D: 27 05    ; If equal, branch
        STAA    M00A0                    *F69F: 97 A0    ; Store A there
        INC     >M009E                   *F6A1: 7C 00 9E ; Increase mem
ZF6A4   TIM     #$04,JMode               *F6A4: 7B 04 CA ; Test mem bit 2
        BEQ     ZF6AC                    *F6A7: 27 03    ; Branch if clear
        JMP     ZF7A6                    *F6A9: 7E F7 A6 ; Jump to below
ZF6AC   LDAA    M009F                    *F6AC: 96 9F    ; Load mem to AccA
        CMPA    M00A9                    *F6AE: 91 A9    : Compare A to mem
        BNE     ZF6C0                    *F6B0: 26 0E    ; Branch if not eq
        LDAA    MBfP2                    *F6B2: 96 9B    ; Load mem to AccA
        LDAB    MMode                    *F6B4: D6 C9    ; Load mem to AccB
        BITB    #$02                     *F6B6: C5 02    ; Test B bit 1
        BNE     ZF707                    *F6B8: 26 4D    ; If clear, branch
        TSTB                             *F6BA: 5D       ; Test whole B
        BPL     ZF705                    *F6BB: 2A 48    ; Branch if pos.
        JMP     ZF13A                    *F6BD: 7E F1 3A ; Jump far above
ZF6C0   STAA    M00A9                    *F6C0: 97 A9    ; Store A in mem
        TIM     #$02,MMode               *F6C2: 7B 02 C9 ; Test mem bit 1
        BNE     ZF6CC                    *F6C5: 26 05    ; If clear, branch
        LDX     #$FFFF                   *F6C7: CE FF FF ; Set X to $FFFF
        BRA     ZF6EA                    *F6CA: 20 1E    : Branc to below
ZF6CC   LDX     #$0000                   *F6CC: CE 00 00 ; Set X to $0000
        ANDA    #$0F                     *F6CF: 84 0F    ; Low nibble of A
ZF6D1   LDAB    J0Data,X                 *F6D1: E6 A4    ; Load (addr+X)->B
        ANDB    #$0F                     *F6D3: C4 0F    ; Low nibble of B
        CBA                              *F6D5: 11       ; Compare B with A
        BEQ     ZF6F4                    *F6D6: 27 1C    ; If equal, branch
        LDAB    J0Data,X                 *F6D8: E6 A4    ; Load (addr+X)->B
        ASLA                             *F6DA: 48       ; Shift left AccA
        ASLB                             *F6DB: 58       ; Shift left AccB
        RORA                             *F6DC: 46       ; Rotate right A
        STAA    J0Data,X                 *F6DD: A7 A4    ; Put A->(addr+X)
        DEX                              *F6DF: 09       ; Decrease X
        BNE     ZF6E7                    *F6E0: 26 05    ; If not 0, branch
        OIM     #$40,JMode               *F6E2: 72 40 CA ; OR mem with $40
        BRA     ZF6F7                    *F6E5: 20 10    ; Branch to below
ZF6E7   OIM     #$80,JMode               *F6E7: 72 80 CA ; OR mem with $80
ZF6EA   LDAA    M00A9                    *F6EA: 96 A9    ; Load mem to AccA
        LSRA                             *F6EC: 44       ; Bring the high..
        LSRA                             *F6ED: 44       ; ...nibble of...
        LSRA                             *F6EE: 44       ; ...AccA to...
        LSRA                             *F6EF: 44       ; ...low nibble
        INX                              *F6F0: 08       ; Increase X...
        INX                              *F6F1: 08       ; ...twice
        BRA     ZF6D1                    *F6F2: 20 DD    ; Loop
ZF6F4   DEX                              *F6F4: 09       ; Decrease X
        BNE     ZF6EA                    *F6F5: 26 F3    ; If not 0, branch
ZF6F7   LDAA    MBfP2                    *F6F7: 96 9B    ; Load mem to AccA
        LDAB    MMode                    *F6F9: D6 C9    ; Load mem to AccB
        BITB    #$02                     *F6FB: C5 02    ; Test AccB bit 1
        BNE     ZF707                    *F6FD: 26 08    ; If set, branch
        TSTB                             *F6FF: 5D       ; Test all AccB
        BPL     ZF705                    *F700: 2A 03    ; If pos., branch
        JMP     ZF741                    *F702: 7E F7 41 ; Jump to below
ZF705   ORAA    #$FB                     *F705: 8A FB    ; OR A with $FB
ZF707   COMA                             *F707: 43       ; Invert AccA
        CMPA    M00A8                    *F708: 91 A8    ; Compare A to mem
        BEQ     ZF741                    *F70A: 27 35    ; If equal, branch
        STAA    M00A8                    *F70C: 97 A8    ; Store A to mem
        RORA                             *F70E: 46       ; Rotate right A
        LDAB    MMode                    *F70F: D6 C9    ; Load mem to AccB
        BITB    #$02                     *F711: C5 02    ; Test AccB bit 1
        BNE     ZF71C                    *F713: 26 07    ; Branch if not eq
        LDX     #$0001                   *F715: CE 00 01 ; Set X to $0001
        RORA                             *F718: 46       ; Rotate right A
        SEC                              *F719: 0D       ; Set carry bit
        BRA     ZF720                    *F71A: 20 04    ; Branch to below
ZF71C   LDX     #$0000                   *F71C: CE 00 00 ; Set X to $0000
        CLC                              *F71F: 0C       ; Clear carry bit
ZF720   RORA                             *F720: 46       ; Rotate A right
        LDAB    J0Data,X                 *F721: E6 A4    ; Load (addr+X)->B
        BCC     ZF72B                    *F723: 24 06    ; No Carry? Branch
        BMI     ZF737                    *F725: 2B 10    ; Negative? Branch
        ORAB    #$80                     *F727: CA 80    ; OR AccB with $80
        BRA     ZF72F                    *F729: 20 04    ; Branch to below
ZF72B   BPL     ZF737                    *F72B: 2A 0A    ; Positive? Branch
        ANDB    #$7F                     *F72D: C4 7F    ; Mask out top bit
ZF72F   STAB    J0Data,X                 *F72F: E7 A4    ; Put B->(addr+X)
        TSTA                             *F731: 4D       ; Test AccA
        BMI     ZF73E                    *F732: 2B 0A    ; Branch if neg.
        OIM     #$80,JMode               *F734: 72 80 CA ; OR mem with $80
ZF737   TSTA                             *F737: 4D       ; Test AccA
        BMI     ZF741                    *F738: 2B 07    ; Branch if neg.
        INX                              *F73A: 08       ; Increase X
        SEC                              *F73B: 0D       ; Set carry bit
        BRA     ZF720                    *F73C: 20 E2    ; Branch to above
ZF73E   OIM     #$40,JMode               *F73E: 72 40 CA : OR mem with $40
ZF741   LDAA    JMode                    *F741: 96 CA    ; Load this to A
        BITA    #$02                     *F743: 85 02    ; Test A bit 1
        BNE     ZF778                    *F745: 26 31    ; If set, branch
        BITA    #$C0                     *F747: 85 C0    ; Test top 2 bits
        BEQ     ZF753                    *F749: 27 08    ; If clear, branch
        BITA    #$08                     *F74B: 85 08    ; Test A bit 3
        BNE     ZF756                    *F74D: 26 07    ; If set, branch
ZF74F   CLI                              *F74F: 0E       ; Enable IRQs
        AIM     #$3F,JMode               *F750: 71 3F CA ; AND mem with $3F
ZF753   JMP     ZF13A                    *F753: 7E F1 3A ; Jump to above
ZF756   BITA    #$80                     *F756: 85 80    ; Test mem bit 7
        BEQ     ZF766                    *F758: 27 0C    ; If clear, branch
        SEI                              *F75A: 0F       ; Disable IRQs
        LDAA    #$FE                     *F75B: 86 FE    ; Load $FE to AccA
        LDAB    #$01                     *F75D: C6 01    ; Load $01 to AccB
        LDX     #J0Data                  *F75F: CE 00 A4 ; Base addr. to X
        JSR     ZFD34                    *F762: BD FD 34 ; Subroutine
        CLI                              *F765: 0E       ; Enable IRQs
ZF766   TIM     #$40,JMode               *F766: 7B 40 CA ; Test mem bit 6
        BEQ     ZF74F                    *F769: 27 E4    ; If clear, branch
        SEI                              *F76B: 0F       ; Disable IRQs
        LDAA    #$FF                     *F76C: 86 FF    ; Load $FF to AccA
        LDAB    #$01                     *F76E: C6 01    ; Load $01 to AccB
        LDX     #J1Data                  *F770: CE 00 A5 ; Base addr. to X
        JSR     ZFD34                    *F773: BD FD 34 ; Subroutine
        BRA     ZF74F                    *F776: 20 D7    ; Branch to above
ZF778   LDAA    >JMonRC                  *F778: B6 00 A7 ; Load mem to AccA
        BNE     ZF74F                    *F77B: 26 D2    ; Not zero? Branch
        LDAA    JMonRR                   *F77D: 96 94    ; Load mem to AccA
        STAA    >JMonRC                  *F77F: B7 00 A7 ; Store A there
        CLRA                             *F782: 4F       ; Clear AccA
        LDAB    J0Data                   *F783: D6 A4    ; Load mem to AccB
        BPL     ZF789                    *F785: 2A 02    ; If pos., branch
        ORAA    #$02                     *F787: 8A 02    ; Set bit 1 in A
ZF789   ASLB                             *F789: 58       ; Shift AccB...
        ASLB                             *F78A: 58       ; ...left so...
        ASLB                             *F78B: 58       ; ...low nibble...
        ASLB                             *F78C: 58       ; ...becomes high
        STAB    M00A9                    *F78D: D7 A9    ; Store B there
        LDAB    J1Data                   *F78F: D6 A5    ; Load mem to AccB
        BPL     ZF795                    *F791: 2A 02    ; If pos., branch
        ORAA    #$01                     *F793: 8A 01    ; Set bit 0 in A
ZF795   ANDB    #$7F                     *F795: C4 7F    ; Mask out top bit
        ORAB    M00A9                    *F797: DA A9    ; OR B with mem
        STAB    M00A9                    *F799: D7 A9    ; Store B there
        SEI                              *F79B: 0F       ; Disable IRQs
        LDAB    #$01                     *F79C: C6 01    ; Set AccB to $01
        LDX     #M00A9                   *F79E: CE 00 A9 ; Base addr. to X
        JSR     ZFD34                    *F7A1: BD FD 34 ; Subroutine
        BRA     ZF74F                    *F7A4: 20 A9    ; Branch to above
ZF7A6   AIM     #$7F,M00A1               *F7A6: 71 7F A1 ; AND mem with $7F
        LDX     #$0000                   *F7A9: CE 00 00 ; Reset X to $0000
        LDAA    #$0C                     *F7AC: 86 0C    ; Load #12 to AccA
        STAA    M00C5                    *F7AE: 97 C5    ; Store A there
ZF7B0   LDAB    M009F                    *F7B0: D6 9F    ; Load mem to AccB
        ANDB    M00C5                    *F7B2: D4 C5    ; AND B with mem
        BNE     ZF7CD                    *F7B4: 26 17    ; Not zero? Branch
        LDAB    M00C5                    *F7B6: D6 C5    ; Load mem to AccB
        BITB    JMonRR                   *F7B8: D5 94    ; Test B for (mem)
        BEQ     ZF7CA                    *F7BA: 27 0E    ; If equal, branch
        CLRA                             *F7BC: 4F       ; Clear AccA
        STAA    J0Data,X                 *F7BD: A7 A4    ; Store A->(mem+X)
        STAA    M00A6,X                  *F7BF: A7 A6    ; Store A->(mem+X)
        STAA    M00A8,X                  *F7C1: A7 A8    ; Store A->(mem+X)
        COMB                             *F7C3: 53       ; Invert AccB
        ANDB    JMonRR                   *F7C4: D4 94    ; And B with mem
        STAB    JMonRR                   *F7C6: D7 94    ; Store mem there
        BSR     ZF7EF                    *F7C8: 8D 25    ; Subroutine
ZF7CA   JMP     ZF85D                    *F7CA: 7E F8 5D ; Jump to below
ZF7CD   CMPB    M00C5                    *F7CD: D1 C5    ; Compare B w. mem
        BNE     ZF7D4                    *F7CF: 26 03    ; Branch if not eq
        JMP     ZF85D                    *F7D1: 7E F8 5D ; Jump to below
ZF7D4   LDAA    JMonRR                   *F7D4: 96 94    ; Load mem to AccA
        ANDA    M00C5                    *F7D6: 94 C5    ; AND A with mem
        CBA                              *F7D8: 11       ; Compare A and B
        BEQ     ZF7FB                    *F7D9: 27 20    ; If equal, branch
        COMA                             *F7DB: 43       ; Invert AccA
        ANDA    JMonRR                   *F7DC: 94 94    : AND A with mem
        ABA                              *F7DE: 1B       ; Add B to A
        STAA    JMonRR                   *F7DF: 97 94    ; Store A there
        BSR     ZF7EF                    *F7E1: 8D 0C    ; Subroutine
        LDAA    #$64                     *F7E3: 86 64    ; Set AccA to #100
        STAA    J0KCodC,X                *F7E5: A7 A2    ; Put A to (mem+X)
        LDAA    JKCodRx,X                *F7E7: A6 95    ; Load (mem+X)->A
        BEQ     ZF837                    *F7E9: 27 4C    ; If zero, branch
        STAA    J0Data,X                 *F7EB: A7 A4    ; Store A->(mem+X)
        BRA     ZF82F                    *F7ED: 20 40    ; Branch to below
ZF7EF   LDAA    M00A1                    *F7EF: 96 A1    ; Load mem to AccA
        BMI     ZF7F6                    *F7F1: 2B 03    ; Branch if neg.
        ANDA    #$DF                     *F7F3: 84 DF    ; AND A with $DF
;
; Again, the following 3 bytes allow dual interpretation, depending
; on from where it is being entered: Lineary or from the branch at $F7F1:
        TST     $84BF                    *F7F5: 7D 84 BF ; Bogus test mem
; or
        FCB     $7D                      *F7F5: 7D       ; Data '}'
ZF7F6   ANDA    #$BF                     *F7F6: 84 BF    ; AND A with $BF
;
        STAA    M00A1                    *F7F8: 97 A1    ; Store A there
        RTS                              *F7FA: 39       ; Return
;
; This seems to be handling joystick keycode mode
ZF7FB   LDAA    M00A1                    *F7FB: 96 A1    ; Load mem to AccA
        BMI     ZF805                    *F7FD: 2B 06    ; If neg., branch
        BITA    #$20                     *F7FF: 85 20    ; Test AccA Bit 5
        BNE     ZF80D                    *F801: 26 0A    ; If set, branch
        BRA     ZF809                    *F803: 20 04    ; Branch always
ZF805   BITA    #$40                     *F805: 85 40    ; Test AccA Bit 4
        BNE     ZF80D                    *F807: 26 04    ; If set, branch
ZF809   LDAB    JKCodRx,X                *F809: E6 95    ; Load (mem+X)->B
        BNE     ZF817                    *F80B: 26 0A    ; Branch if not 0
ZF80D   LDAB    JKCodVx,X                *F80D: E6 99    ; Load (mem+X)->B
        BEQ     ZF85D                    *F80F: 27 4C    ; If zero, branch
        LDAB    M00A8,X                  *F811: E6 A8    ; Load (mem+X)->B
        BNE     ZF85D                    *F813: 26 48    ; If not 0, branch
        BRA     ZF837                    *F815: 20 20    ; Branch to below
ZF817   LDAB    JKCodTx,X                *F817: E6 97    ; Load (mem+X)->B
        BEQ     ZF81F                    *F819: 27 04    ; If zero, branch
        LDAB    M00A6,X                  *F81B: E6 A6    ; Load (mem+X)->B
        BEQ     ZF82B                    *F81D: 27 0C    ; If zero, branch
ZF81F   LDAB    J0Data,X                  *F81F: E6 A4    ; Load (mem+X)->B
        BNE     ZF85D                    *F821: 26 3A    ; Branch if not 0
        BSR     ZF86F                    *F823: 8D 4A    ; Subroutine
        LDAB    JKCodVx,X                *F825: E6 99    ; Load (mem+X)->B
        STAB    M00A8,X                  *F827: E7 A8    ; Store B->(mem+X)
        BRA     ZF85D                    *F829: 20 32    ; Branch to below
ZF82B   LDAB    J0Data,X                 *F82B: E6 A4    ; Load (mem+X)->B
        BEQ     ZF835                    *F82D: 27 06    ; If zero, branch
ZF82F   LDAB    JKCodTx,X                *F82F: E6 97    ; Load (mem+X)->B
        STAB    M00A6,X                  *F831: E7 A6    ; Store B->(mem+X)
        BRA     ZF83B                    *F833: 20 06    : Branch to below
ZF835   BSR     ZF86F                    *F835: 8D 38    ; Subroutine
ZF837   LDAB    JKCodVx,X                *F837: E6 99    ; Load (mem+X)->B
        STAB    M00A8,X                  *F839: E7 A8    ; Store B->(mem+X)
ZF83B   LDAB    JMonRR                   *F83B: D6 94    ; Load mem to AccB
        LDX     #MF87A                   *F83D: CE F8 7A ; Base addr. to X
        LDAA    M00A1                    *F840: 96 A1    : Load mem to AccA
        BMI     ZF848                    *F842: 2B 04    ; If neg., branch
        INX                              *F844: 08       ; Increase X...
        INX                              *F845: 08       ; ...twice
        LSRB                             *F846: 54       ; Shift B right...
        LSRB                             *F847: 54       ; ...twice...
ZF848   LSRB                             *F848: 54       ; Once or 3 times
        ANDB    #$01                     *F849: C4 01    ; Only lowest bit
        ABX                              *F84B: 3A       ; Add AccB to X
        LDAA    ,X                       *F84C: A6 00    ; Read mem(X)->A
        SEI                              *F84E: 0F       ; Disable IRQs
        TAB                              *F84F: 16       ; Transfer A->B
        ORAB    #$80                     *F850: CA 80    ; Set AccB bit 7
        STAB    M00C6                    *F852: D7 C6    ; Store B there
        LDX     #M00C6                   *F854: CE 00 C6 ; Base addr. to X
        LDAB    #$01                     *F857: C6 01    ; Set AccB to $01
        JSR     ZFD34                    *F859: BD FD 34 ; Subroutine
        CLI                              *F85C: 0E       ; Enable IRQs
ZF85D   LDAA    M00A1                    *F85D: 96 A1    ; Load mem to AccA
        BMI     ZF87E                    *F85F: 2B 1D    ; Branch if neg.
        ORAA    #$80                     *F861: 8A 80    ; Set AccA bit 7
        STAA    M00A1                    *F863: 97 A1    ; Store A there
        LDAA    #$03                     *F865: 86 03    ; Set AccA to $03
        STAA    M00C5                    *F867: 97 C5    ; Store A there
        LDX     #P2DDR                   *F869: CE 00 01 ; Set X to $0001
        JMP     ZF7B0                    *F86C: 7E F7 B0 ; Jump far down
ZF86F   TSTA                             *F86F: 4D       ; Test AccA
        BMI     ZF875                    *F870: 2B 03    ; If neg., branch
        ORAA    #$20                     *F872: 8A 20    ; Set AccA bit 5
;
; Once more, this allows dual interpretation, depending on from where it
; is being entered: Either lineary or from the branch at $F870:
        TST     $8A40                    *F874: 7D 8A 40 ; Bogus test mem
; or
        FCB     $7D                      *F874: 7D       ; Data '}'
ZF875   ORAA    #$40                     *F875: 8A 40    ; Set AccA bit 6
;
        STAA    M00A1                    *F877: 97 A1    ; Store A there
        RTS                              *F879: 39       ; Return
;
; Table with data for joystick keycode mode
MF87A   FCB     $48                      *F87A: 48       ; Cursor Up
        FCB     $50                      *F87B: 50       ; Cursor Down
        FCB     $4B                      *F87C: 4B       ; Cursor Left
        FCB     $4D                      *F87D: 4D       ; Cursor Right

ZF87E   LDAA    #$74                     *F87E: 86 74    ; Set AccA to $74
        LDAB    M00A1                    *F880: D6 A1    ; Load mem to AccB
        TIM     #$02,MBfP2               *F882: 7B 02 9B ; Test mem bit 1
        BNE     ZF88F                    *F885: 26 08    ; If set, branch
        BITB    #$02                     *F887: C5 02    ; Test AccB bit 1
        BNE     ZF89F                    *F889: 26 14    ; If set, branch
        ORAB    #$02                     *F88B: CA 02    ; Set Bit 1 of B
        BRA     ZF897                    *F88D: 20 08    ; Branch to below
ZF88F   BITB    #$02                     *F88F: C5 02    ; Test AccB bit 1
        BEQ     ZF89F                    *F891: 27 0C    ; If zero, branch
        ANDB    #$FD                     *F893: C4 FD    ; AND B with $FD
        ORAA    #$80                     *F895: 8A 80    ; Set Bit 7 of A
ZF897   STAB    M00A1                    *F897: D7 A1    : Store B there
        SEI                              *F899: 0F       ; Disable IRQs
        CLRB                             *F89A: 5F       ; Clear AccB
        JSR     ZFD34                    *F89B: BD FD 34 ; Subroutine
        CLI                              *F89E: 0E       ; Enable IRQs
ZF89F   JMP     ZF13A                    *F89F: 7E F1 3A ; Jump to above
ZF8A2   TIM     #$10,M00CB               *F8A2: 7B 10 CB ; Test mem bit 4
        BNE     ZF8D1                    *F8A5: 26 2A    ; If set, branch
        LDAB    M00D7                    *F8A7: D6 D7    ; Load mem to AccB
        BPL     ZF8D1                    *F8A9: 2A 26    ; If pos., branch
        LDAA    #$16                     *F8AB: 86 16    ; Set AccA to $16
ZF8AD   DECA                             *F8AD: 4A       ; Decrease AccA
        BNE     ZF8AD                    *F8AE: 26 FD    ; If not 0, loop
ZF8B0   LDAA    P2DAT                    *F8B0: 96 03    ; Load P2DAT to A
        CMPA    P2DAT                    *F8B2: 91 03    ; Check again
        BNE     ZF8B0                    *F8B4: 26 FA    ; Loop if mismatch
        BITA    #$04                     *F8B6: 85 04    ; Test A bit 2
        BEQ     ZF8BB                    *F8B8: 27 01    ; If clear, branch
        TST     $0D,X                    *F8BA: 6D 0D    ; Test (mem+X)
        LDAA    J0Data                   *F8BC: 96 A4    ; Load mem to AccA
        ROLA                             *F8BE: 49       ; Rotate AccA left
        STAA    J0Data                   *F8BF: 97 A4    ; Store A there
        DEC     >J1Data                  *F8C1: 7A 00 A5 ; Decrease mem
        BNE     ZF8D1                    *F8C4: 26 0B    ; If not 0, branch
        LDAB    #$08                     *F8C6: C6 08    ; Set AccB to $08
        STAB    J1Data                   *F8C8: D7 A5    ; Store B there
ZF8CA   TIM     #$20,TRCSR               *F8CA: 7B 20 11 ; Check TDRE
        BEQ     ZF8CA                    *F8CD: 27 FB    ; If clear, branch
        STAA    TXB                      *F8CF: 97 13    ; Store A in TxBuf
ZF8D1   JMP     ZF13A                    *F8D1: 7E F1 3A ; Jump to above
;
; Subroutine to pre-interpret serial receive data, i.e. IKBD command
ZF8D4   AIM     #$78,M00CB               *F8D4: 71 78 CB ; Unset ctrl-bits
        LDAB    RxDat0                   *F8D7: D6 CD    ; Load mem to AccB
        TBA                              *F8D9: 17       ; Transfer B->A
        BPL     ZF8F3                    *F8DA: 2A 17    ; If pos., branch
        CMPB    #$80                     *F8DC: C1 80    ; Compare B to $80
        BNE     ZF8E3                    *F8DE: 26 03    ; Branch if not eq
        JMP     ZF990                    *F8E0: 7E F9 90 ; Jump to below
ZF8E3   CMPB    #$87                     *F8E3: C1 87    ; Compare B to $87
        BCS     ZF916                    *F8E5: 25 2F    ; If lower, branch
        CMPB    #$9B                     *F8E7: C1 9B    ; Compare B to $9B
        BCC     ZF916                    *F8E9: 24 2B    ; Branch if higher
        ANDB    #$7F                     *F8EB: C4 7F    ; Mask out top bit
        SUBB    #$07                     *F8ED: C0 07    ; Sub. 7 from AccB
        ADDB    #$1C                     *F8EF: CB 1C    ; Add $1C to AccB
        BRA     ZF8FD                    *F8F1: 20 0A    ; Branch to below
; Received IKBD command is < $80 meaning not a status inquiry, so interpret
ZF8F3   CMPB    #$07                     *F8F3: C1 07    ; Check B for $07
        BCS     ZF916                    *F8F5: 25 1F    ; Invalid command!
        CMPB    #$23                     *F8F7: C1 23    ; Compare B to $23
        BCC     ZF916                    *F8F9: 24 1B    ; Invalid command!
        SUBB    #$07                     *F8FB: C0 07    ; Sub. 7 from B
ZF8FD   ASLB                             *F8FD: 58       ; Multiply B x 2
        LDX     #MF930                   *F8FE: CE F9 30 ; Base addr. to X
        ABX                              *F901: 3A       ; Add AccB to X
        LDX     ,X                       *F902: EE 00    ; Load mem(X) to X
        BEQ     ZF916                    *F904: 27 10    ; If zero, branch
        BITA    #$80                     *F906: 85 80    ; Test AccA Bit 7
        BEQ     ZF914                    *F908: 27 0A    ; If zero, branch
        TIM     #$08,M00CB               *F90A: 7B 08 CB ; Test mem bit 3
        BNE     ZF916                    *F90D: 26 07    ; If set, branch
        TIM     #$03,JMode               *F90F: 7B 03 CA ; Test mem bit 1,0
        BNE     ZF916                    *F912: 26 02    ; Branch if set
ZF914   JMP     ,X                       *F914: 6E 00    ; Jump to mem(X)
ZF916   AIM     #$18,M00CB               *F916: 71 18 CB ; AND mem with $18
        BRA     ZF929                    *F919: 20 0E    ; Branch to below
ZF91B   TIM     #$08,M00CB               *F91B: 7B 08 CB ; Test mem bit 3
        BEQ     ZF929                    *F91E: 27 09    ; Branch if clear
        AIM     #$F7,M00CB               *F920: 71 F7 CB ; AND mem with $F7
        OIM     #$08,MMode               *F923: 72 08 C9 ; OR mem with $08
        OIM     #$04,TRCSR               *F926: 72 04 11 ; Enable Tx-IRQ
ZF929   CLR     >RxCnt                   *F929: 7F 00 CC ; Clear mem
        OIM     #$10,TRCSR               *F92C: 72 10 11 ; Enable Rx-IRQ
        RTS                              *F92F: 39       ; Return
;
; Jump table to interpret serial received data
MF930   FCD     $FAA4                    *F930: FA A4    ; $07:Set MB actn.
        FCD     $FAB9                    *F932: FA B9    ; $08:Set rel Mpos 
        FCD     $FACB                    *F934: FA CB    ; $09:Set abs Mpos
        FCD     $FAE8                    *F936: FA E8    ; $0A:Set Mkeycode
        FCD     $FB0B                    *F938: FB 0B    ; $0B:Set Mthresh
        FCD     $FB25                    *FB3A: FB 25    ; $0C:Set Mscale
        FCD     $FB39                    *FB3C: FB 39    ; $0D:Intergt.Mpos
        FCD     $FB5F                    *FB3E: FB 5F    ; $0E:Load Mpos
        FCD     $FB7C                    *F940: FB 7C    ; $0F:Set Y0=bot.
        FCD     $FB82                    *F942: FB 82    ; $10:Set Y0=top
        FCD     $F91B                    *F944: F9 1B    ; $11:Resume
        FCD     $FB88                    *F946: FB 88    ; $12:Disable M
        FCD     $F9AF                    *F948: F9 AF    ; $13:Pause outp.
        FCD     $F9C1                    *F94A: F9 C1    ; $14:Set Jev.rep.
        FCD     $F9C5                    *F94C: F9 C5    ; $15:Set Jin mode
        FCD     $F9CC                    *F94E: F9 CC    ; $16:Jinterrogate
        FCD     $F9F3                    *F950: F9 F3    ; $17:Set Jmon.
        FCD     $FA12                    *F952: FA 12    ; $18:Set FButMon.
        FCD     $FA21                    *F954: FA 21    ; $19:Set Jkeycode
        FCD     $FA41                    *F956: FA 41    ; $1A:Disable J
        FCD     $FA5B                    *F958: FA 5B    ; $1B:Set Time
        FCD     $FA95                    *F95A: FA 95    ; $1C:Intrrgt.Time
        FCD     $0000                    *F95C: 00 00    ; unused
        FCD     $0000                    *F95E: 00 00    ; unused
        FCD     $0000                    *F960: 00 00    ; unused
        FCD     $FBD4                    *F962: FB D4    ; $20:Mem.load
        FCD     $FC16                    *F964: FC 16    ; $21:Mem.read
        FCD     $FC3B                    *F966: FC 3B    ; $22:Mem.excecute

        FCD     $FC59                    *F968: FC 59    ; $87:Mb actn?
        FCD     $FC62                    *F96A: FC 62    ; $88:M mode?
        FCD     $FC62                    *F96C: FC 62    ; $89:M mode?
        FCD     $FC62                    *F96E: FC 62    ; $8A:M mode?
        FCD     $FC83                    *F970: FC 83    ; $8B:M thresh?
        FCD     $FC8C                    *F972: FC 8C    ; $8C:M scale?
        FCD     $0000                    *F974: 00 00    ; unused
        FCD     $0000                    *F976: 00 00    ; unused
        FCD     $FC95                    *F978: FC 95    ; $8F:Mvert.coord?
        FCD     $FC95                    *F97A: FC 95    ; $90:Mvert.coord?
        FCD     $0000                    *F97C: 00 00    ; unused
        FCD     $FCA2                    *F97E: FC A2    ; $92:Menable?
        FCD     $0000                    *F980: 00 00    ; unused
        FCD     $FCAE                    *F982: FC AE    ; $94:Jev mode?
        FCD     $FCAE                    *F984: FC AE    ; $95:Jin mode?
        FCD     $0000                    *F986: 00 00    ; unused
        FCD     $0000                    *F988: 00 00    ; unused
        FCD     $0000                    *F98A: 00 00    ; unused
        FCD     $FCAE                    *F98C: FC AE    ; $99:Jev mode?
        FCD     $FCC9                    *F98E: FC C9    ; $9A:J disable?
; 
; This code snippets handles a software reset sequence ($80, $01)
ZF990   AIM     #$EF,TRCSR               *F990: 71 EF 11 ; Unset RxIE
        LDAB    #$02                     *F993: C6 02    ; Set AccB to 2
        JSR     ZFCFE                    *F995: BD FC FE ; 2 Bytes recvd.?
        BCC     ZF9AB                    *F998: 24 11    ; If not, branch
        LDAA    RxDat1                   *F99A: 96 CE    ; Check Rx-byte 1
        CMPA    #$01                     *F99C: 81 01    ; Is it a $01?
        BNE     ZF9A8                    *F99E: 26 08    ; If not, skip
        LDS     #$00FF                   *F9A0: 8E 00 FF ; Reset stack
        LDX     #ZF010                   *F9A3: CE F0 10 ; Set $F010 as...
        PSHX                             *F9A6: 3C       ; ... return addr.
        RTS                              *F9A7: 39       ; Software reset!
; 2 Bytes received but not a valid reset sequence
ZF9A8   JMP     ZF929                    *F9A8: 7E F9 29 ; Jump to above
; More than 2 bytes recived - potentially other data follows
ZF9AB   OIM     #$10,TRCSR               *F9AB: 72 10 11 ; Set RxIE again
        RTS                              *F9AE: 39       ; Return
;
; IKBD command $13: Pause output
ZF9AF   TIM     #$08,M00CB               *F9AF: 7B 08 CB ; Test mem for $08
        BNE     ZF9BE                    *F9B2: 26 0A    ; Branch if clear
        OIM     #$08,M00CB               *F9B4: 72 08 CB ; Set mem bit 3
        AIM     #$F7,MMode               *F9B7: 71 F7 C9 ; Clear mem bit 3
        LDAA    TxNo                     *F9BA: 96 D5    ; Load mem to AccA
        STAA    TxLim                    *F9BC: 97 D8    ; Store A in mem
ZF9BE   JMP     ZF929                    *F9BE: 7E F9 29 ; Jump to above
;
; IKBD command $14: Set joystick event reporting
ZF9C1   LDAA    #$28                     *F9C1: 86 28    ; Set AccA to $28
        BRA     ZF9C7                    *F9C3: 20 02    ; Branch to below
;
; IKBD command $15: Set joystick interrogation mode
ZF9C5   LDAA    #$30                     *F9C5: 86 30    ; Set AccA to $30
ZF9C7   STAA    JMode                    *F9C7: 97 CA    ; Store A in mem
        JMP     ZFA47                    *F9C9: 7E FA 47 ; Jump to below
;
; IKBD command $16: Joystick interrogation
ZF9CC   LDAA    JMode                    *F9CC: 96 CA    ; Load mem to AccA
        BITA    #$20                     *F9CE: 85 20    ; Test mem bit 5
        BNE     ZF9D5                    *F9D0: 26 03    ; If set, branch
        JMP     ZF929                    *F9D2: 7E F9 29 ; Jump to above
ZF9D5   BITA    #$18                     *F9D5: 85 18    ; Test A bits 3,4
        BEQ     ZF9F0                    *F9D7: 27 17    ; Branch if clear
        TIM     #$02,MMode               *F9D9: 7B 02 C9 ; Test mem bit 1
        BNE     ZF9E1                    *F9DC: 26 03    ; If set, branch
        CLR     >J0Data                  *F9DE: 7F 00 A4 ; Clear mem byte
ZF9E1   SEI                              *F9E1: 0F       ; Disable IRQs
        LDAA    #$FD                     *F9E2: 86 FD    ; Set AccA to $FD
        LDAB    #$02                     *F9E4: C6 02    ; Set AccB to $02
        LDX     #J0Data                  *F9E6: CE 00 A4 ; Base addr. to X
        JSR     ZFD34                    *F9E9: BD FD 34 ; Subroutine
        CLI                              *F9EC: 0E       ; Enable IRQs
        JMP     ZF91B                    *F9ED: 7E F9 1B ; Jump to above
ZF9F0   JMP     ZF929                    *F9F0: 7E F9 29 ; Jump to above
;
; IKBD command $17: Set joystick monitoring
ZF9F3   LDAB    #$02                     *F9F3: C6 02    ; Set AccB to 2
        JSR     ZFCFE                    *F9F5: BD FC FE ; Subroutine
        BCC     ZFA0E                    *F9F8: 24 14    ; No carry? Branch
        AIM     #$F8,M00CB               *F9FA: 71 F8 CB ; AND mem with $F8
        LDAA    RxDat1                   *F9FD: 96 CE    ; Load mem to AccA
        STAA    JMonRR                   *F9FF: 97 94    ; Store A in mem
        STAA    JMonRC                   *FA01: 97 A7    ; Store A in mem
        LDAA    #$0A                     *FA03: 86 0A    ; Set AccA to #10
        STAA    M00A6                    *FA05: 97 A6    ; Store A in mem
        LDAA    #$22                     *FA07: 86 22    ; Set AccA to #34
        STAA    JMode                    *FA09: 97 CA    ; Store A in mem
        JMP     ZFA47                    *FA0B: 7E FA 47 ; Jump to below
ZFA0E   OIM     #$10,TRCSR               *FA0E: 72 10 11 ; Enable Rx-IRQ
        RTS                              *FA11: 39       ; Return
;
; IKBD command $18: Set fire button monitoring
ZFA12   LDAA    #$21                     *FA12: 86 21    ; Set AccA to $21
        STAA    JMode                    *FA14: 97 CA    ; Store A in mem
        OIM     #$02,MMode               *FA16: 72 02 C9 ; Set Bit 1 in mem
        LDD     #TCSR                    *FA19: CC 00 08 ; Set D to $0008
        STD     J0Data                   *FA1C: DD A4    ; Store D in mem
        JMP     ZF91B                    *FA1E: 7E F9 1B ; Jump to above
;
; IKBD command $19: Set joystick keycode mode
ZFA21   LDAB    #$07                     *FA21: C6 07    ; Set AccB to $07
        JSR     ZFCFE                    *FA23: BD FC FE ; Subroutine
        BCC     ZFA3D                    *FA26: 24 15    ; No carry? Branch
        LDX     #JKCodRx                 *FA28: CE 00 95 ; Base addr. to X
        JSR     ZFD1E                    *FA2B: BD FD 1E ; Subroutine
        CLRA                             *FA2E: 4F       ; Clear AccA
        CLRB                             *FA2F: 5F       ; Clear AccB
        STAA    JMonRR                   *FA30: 97 94    ; Store A here
        STAA    M00A1                    *FA32: 97 A1    ; Store A there
        STD     J0KCodC                  *FA34: DD A2    ; Store D in mem
        LDAA    #$24                     *FA36: 86 24    ; Set AccA to $24
        STAA    JMode                    *FA38: 97 CA    ; Store A in mem
        JMP     ZFA47                    *FA3A: 7E FA 47 ; Jump to below
ZFA3D   OIM     #$10,TRCSR               *FA3D: 72 10 11 ; Enable Rx-IRQ
        RTS                              *FA40: 39       ; Return
;
; IKBD command $1A: Disable joysticks
ZFA41   AIM     #$DF,JMode               *FA41: 71 DF CA ; Clear mem bit 5
        JMP     ZF91B                    *FA44: 7E F9 1B ; Jump to above
;
ZFA47   CLRA                             *FA47: 4F       ; Clear AccA
        CLRB                             *FA48: 5F       ; Clear AccB
        STD     J0Data                   *FA49: DD A4    ; Store D here
        STD     M009D                    *FA4B: DD 9D    ; Store D there
        STD     M00A8                    *FA4D: DD A8    ; Store D here
        STAA    M009F                    *FA4F: 97 9F    ; Store A there
        LDAA    #$06                     *FA51: 86 06    ; Set AccA to $06
        STAA    MBfP2                    *FA53: 97 9B    ; Store A in mem
        OIM     #$02,MMode               *FA55: 72 02 C9 ; Set mem bit 1
        JMP     ZF91B                    *FA58: 7E F9 1B : Jump to above
;
; IKBD command $1B: Set time-of-day clock
ZFA5B   LDAB    #$07                     *FA5B: C6 07    ; Set AccB to $07
        JSR     ZFCFE                    *FA5D: BD FC FE ; Check # Rx-bytes
        BCC     ZFA91                    *FA60: 24 2F    ; Invalid command
        AIM     #$F8,M00CB               *FA62: 71 F8 CB ; AND mem with $F8
        SEI                              *FA65: 0F       ; Disable IRQs
        CLRB                             *FA66: 5F       ; Reset AccB
ZFA67   LDX     #RxDat1                  *FA67: CE 00 CE ; Base addr. to X
        ABX                              *FA6A: 3A       ; Add AccB to X
        LDAA    ,X                       *FA6B: A6 00    ; Read mem(X) to A
        ANDA    #$0F                     *FA6D: 84 0F    ; AND A with $0F
        CMPA    #$0A                     *FA6F: 81 0A    ; Check A for $0A
        BCC     ZFA83                    *FA71: 24 10    ; Branch if no BCD
        LDAA    ,X                       *FA73: A6 00    ; Load mem(X) to A
        ANDA    #$F0                     *FA75: 84 F0    ; AND A with $F0
        CMPA    #$A0                     *FA77: 81 A0    ; Check A for $0A
        BCC     ZFA83                    *FA79: 24 08    ; Branch if no BCD
        LDAA    ,X                       *FA7B: A6 00    ; Load mem(X) to A
        LDX     #TodYr                   *FA7D: CE 00 82 ; Base addr. to X
        ABX                              *FA80: 3A       ; Add AccB to X
        STAA    ,X                       *FA81: A7 00    ; Store B->mem(X)
ZFA83   INCB                             *FA83: 5C       ; Increase AccB
        CMPB    #$06                     *FA84: C1 06    ; Is B at limit?
        BNE     ZFA67                    *FA86: 26 DF    ; Loop if not yet
        LDX     #$03E8                   *FA88: CE 03 E8 ; Set X to 1000
        STX     Cnt1ms                   *FA8B: DF 80    ; Store X in mem
        CLI                              *FA8D: 0E       : Enable IRQs
        JMP     ZF91B                    *FA8E: 7E F9 1B ; Jump to above
ZFA91   OIM     #$10,TRCSR               *FA91: 72 10 11 ; Enable Rx-IRQ
        RTS                              *FA94: 39       ; Return
;
; IKBD command $1C: Interrogate time-of-day clocks
ZFA95   SEI                              *FA95: 0F       ; Disable IRQs
        LDAB    #$06                     *FA96: C6 06    ; Answer 6 bytes
        LDAA    #$FC                     *FA98: 86 FC    ; Set AccA to $FC
        LDX     #TodYr                   *FA9A: CE 00 82 ; Base addr. to X
        JSR     ZFD34                    *FA9D: BD FD 34 ; Send Tx-Data
        CLI                              *FAA0: 0E       ; Enable IRQs
        JMP     ZF91B                    *FAA1: 7E F9 1B ; Jump to above
;
; IKBD command $07: Set mouse button action
ZFAA4   LDAB    #$02                     *FAA4: C6 02    ; Set AccB to $02
        JSR     ZFCFE                    *FAA6: BD FC FE ; Subroutine
        BCC     ZFAB5                    *FAA9: 24 0A    ; No carry? Branch
        AIM     #$F8,M00CB               *FAAB: 71 F8 CB ; AND mem with $F8
        LDAA    RxDat1                   *FAAE: 96 CE    ; Load mem to AccA
        STAA    MBActn                   *FAB0: 97 B4    ; Store A there
        JMP     ZF91B                    *FAB2: 7E F9 1B ; Jump to above
ZFAB5   OIM     #$10,TRCSR               *FAB5: 72 10 11 ; Enable Rx-IRQ
        RTS                              *FAB8: 39       ; Return
;
; IKBD command $08: Set relative mouse position reporting
ZFAB9   JSR     ZFB8E                    *FAB9: BD FB 8E ; Subroutine
        AIM     #$0F,MMode               *FABC: 71 0F C9 ; AND mem with $0F
        OIM     #$90,MMode               *FABF: 72 90 C9 ; OR mem with $90
        CLR     >MRelDy                  *FAC2: 7F 00 BD ; Clear mem byte
        CLR     >MRelDx                  *FAC5: 7F 00 BC ; Clear mem byte
        JMP     ZFBAF                    *FAC8: 7E FB AF ; Jump to below
;
; IKBD command $09: Set absolute mouse positioning
ZFACB   LDAB    #$05                     *FACB: C6 05    ; Set AccB to $05
        JSR     ZFCFE                    *FACD: BD FC FE ; Subroutine
        BCC     ZFAE4                    *FAD0: 24 12    ; No carry? Branch
        LDX     #MAbMaxX                 *FAD2: CE 00 AA ; Base addr. to X
        JSR     ZFD1E                    *FAD5: BD FD 1E ; Subroutine
        JSR     ZFB8E                    *FAD8: BD FB 8E ; Subroutine
        AIM     #$0F,MMode               *FADB: 71 0F C9 ; AND mem with $0F
        OIM     #$A0,MMode               *FADE: 72 A0 C9 ; OR mem with $A0
        JMP     ZFBAF                    *FAE1: 7E FB AF ; Jump to below
ZFAE4   OIM     #$10,TRCSR               *FAE4: 72 10 11 ; Enable Rx-IRQ
        RTS                              *FAE7: 39       ; Return
;
; IKBD command $0A: Set mouse keycode mode
ZFAE8   LDAB    #$03                     *FAE8: C6 03    ; Set AccB to $03
        JSR     ZFCFE                    *FAEA: BD FC FE ; Subroutine
        BCC     ZFB07                    *FAED: 24 18    ; No carry? Branch
        LDX     #MKCodDx                 *FAEF: CE 00 AE ; Base addr. to X
        JSR     ZFD1E                    *FAF2: BD FD 1E ; Subroutine
        JSR     ZFB8E                    *FAF5: BD FB 8E ; Subroutine
        AIM     #$0F,MMode               *FAF8: 71 0F C9 ; AND mem with $0F
        OIM     #$C0,MMode               *FAFB: 72 C0 C9 ; OR mem with $C0
        CLR     >M00BA                   *FAFE: 7F 00 BA ; Clear mem byte
        CLR     >M00BB                   *FB01: 7F 00 BB ; Clear mem byte
        JMP     ZFBAF                    *FB04: 7E FB AF ; Jump to below
ZFB07   OIM     #$10,TRCSR               *FB07: 72 10 11 ; Enable Rx-IRQ
        RTS                              *FB0A: 39       ; Return
;
; IKBD command $0B: Set mouse threshold
ZFB0B   LDAB    #$03                     *FB0B: C6 03    ; Set AccB to $03
        JSR     ZFCFE                    *FB0D: BD FC FE ; Subroutine
        BCC     ZFB21                    *FB10: 24 0F    ; No carry? Branch
        LDX     #MEvThrX                 *FB12: CE 00 B0 ; Base addr. to X
        JSR     ZFD1E                    *FB15: BD FD 1E ; Subroutine
        CLR     >MRelDx                  *FB18: 7F 00 BC ; Clear mem byte
        CLR     >MRelDy                   *FB1B: 7F 00 BD ; Clear mem byte
        JMP     ZF91B                    *FB1E: 7E F9 1B ; Jump to above
ZFB21   OIM     #$10,TRCSR               *FB21: 72 10 11 ; Enable Rx-IRQ
        RTS                              *FB24: 39       ; Return
;
; IKBD command $0C: Set mouse scale
ZFB25   LDAB    #$03                     *FB25: C6 03    ; Set AccB to $03
        JSR     ZFCFE                    *FB27: BD FC FE ; Subroutine
        BCC     ZFB35                    *FB2A: 24 09    ; No carry? Branch
        LDX     #MAbsScX                 *FB2C: CE 00 B2 ; Base addr. to X
        JSR     ZFD1E                    *FB2F: BD FD 1E ; Subroutine
        JMP     ZF91B                    *FB32: 7E F9 1B ; Jump to above
ZFB35   OIM     #$10,TRCSR               *FB35: 72 10 11 ; Enable Rx-IRQ
        RTS                              *FB38: 39       ; Return
;
; IKBD command $0D: Interrogate mouse position
ZFB39   LDAA    MMode                    *FB39: 96 C9    ; Load mem to AccA
        BITA    #$02                     *FB3B: 85 02    ; Test A bit 1
        BNE     ZFB5C                    *FB3D: 26 1D    ; If set, branch
        TSTA                             *FB3F: 4D       ; Test AccA
        BPL     ZFB5C                    *FB40: 2A 1A    ; If pos., branch
        BITA    #$20                     *FB42: 85 20    ; Test A bit 5
        BEQ     ZFB5C                    *FB44: 27 16    ; Branch if clear
        SEI                              *FB46: 0F       ; Disable IRQs
        LDAA    M00C2                    *FB47: 96 C2    ; Load mem to AccA
        STAA    MBEvnt                   *FB49: 97 B5    ; Store A in mem
        LDAA    #$F7                     *FB4B: 86 F7    ; Set AccA to $F7
        LDAB    #$05                     *FB4D: C6 05    ; Set AccB to $05
        LDX     #MBEvnt                  *FB4F: CE 00 B5 ; Base addr. to X
        JSR     ZFD34                    *FB52: BD FD 34 ; Subroutine
        CLI                              *FB55: 0E       ; Enable IRQs
        AIM     #$F0,M00C2               *FB56: 71 F0 C2 ; AND mem with $F0
        JMP     ZF91B                    *FB59: 7E F9 1B ; Jump to above
ZFB5C   JMP     ZF929                    *FB5C: 7E F9 29 ; Jump to above
;
; IKBD command $0E: Load mouse position
ZFB5F   LDAB    #$06                     *FB5F: C6 06    ; Set AccB to $06
        JSR     ZFCFE                    *FB61: BD FC FE ; Subroutine
        BCC     ZFB78                    *FB64: 24 12    ; No carry? Branch
        LDX     #MBEvnt                  *FB66: CE 00 B5 ; Base addr. to X
        JSR     ZFD1E                    *FB69: BD FD 1E ; Subroutine
        AIM     #$F0,M00C2               *FB6C: 71 F0 C2 ; AND mem with $F0
        AIM     #$0F,MMode               *FB6F: 71 0F C9 ; AND mem with $0F
        OIM     #$A0,MMode               *FB72: 72 A0 C9 ; OR mem with $A0
        JMP     ZF91B                    *FB75: 7E F9 1B ; Jump to above
ZFB78   OIM     #$10,TRCSR               *FB78: 72 10 11 ; Enable Rx-IRQ
        RTS                              *FB7B: 39       ; Return
;
; IKBD command $0F: Set Y=0 at bottom
ZFB7C   OIM     #$01,MMode               *FB7C: 72 01 C9 ; OR mem with $01
        JMP     ZF91B                    *FB7F: 7E F9 1B ; Jump to above
;
; IKBD command $10: Set Y=0 at top
ZFB82   AIM     #$FE,MMode               *FB82: 71 FE C9 ; AND mem with $FE
        JMP     ZF91B                    *FB85: 7E F9 1B ; Jump to above
;
; IKBD command $12: Disable mouse 
ZFB88   AIM     #$7F,MMode               *FB88: 71 7F C9 ; AND mem with $7F
        JMP     ZF91B                    *FB8B: 7E F9 1B ; Jump to above
;
; Subroutine to read mouse movement and mouse/joystick buttons
ZFB8E   LDAA    P4DAT                    *FB8E: 96 07    ; Load P4Data to A
        TAB                              *FB90: 16       ; Transfer A to B
        ANDA    #$03                     *FB91: 84 03    ; AND A with $03
        STAA    MXraw                    *FB93: 97 BE    ; Store A in mem
        LSRB                             *FB95: 54       ; Shift B right
        LSRB                             *FB96: 54       ; Shift B right
        ANDB    #$03                     *FB97: C4 03    ; AND B with $03
        STAB    MYraw                    *FB99: D7 BF    ; Store B in mem
        CLRB                             *FB9B: 5F       ; Clear AccB
        STAB    M009D                    *FB9C: D7 9D    ; Store B in mem
        LDAA    P2DAT                    *FB9E: 96 03    ; Load P2Data
        ANDA    #$06                     *FBA0: 84 06    ; Buttons only
        STAA    MBfP2                    *FBA2: 97 9B    ; Store A in mem
        BEQ     ZFBAA                    *FBA4: 27 04    ; Both pressed? Go
        CMPA    #$06                     *FBA6: 81 06    ; Both idle?
        BNE     ZFBAC                    *FBA8: 26 02    ; If not, branch
ZFBAA   EORA    #$06                     *FBAA: 88 06    ; Invert buttons
ZFBAC   STAA    MBraw                    *FBAC: 97 C0    ; Store buttons
        RTS                              *FBAE: 39       ; Return
;
; Continued code to cleanly terminate setting a certain mouse mode
ZFBAF   AIM     #$FD,MMode               *FBAF: 71 FD C9 ; AND mem with $FD
        TIM     #$07,JMode               *FBB2: 7B 07 CA ; Test mem for $07
        BNE     ZFBC5                    *FBB5: 26 0E    ; If set, branch
        AIM     #$F0,M009F               *FBB7: 71 F0 9F ; AND mem with $F0
        AIM     #$F0,M00A9               *FBBA: 71 F0 A9 ; AND mem with $F0
        AIM     #$F0,M00A0               *FBBD: 71 F0 A0 ; AND mem with $F0
        AIM     #$04,M00A8               *FBC0: 71 04 A8 ; AND mem with $04
        BRA     ZFBD1                    *FBC3: 20 0C    ; Branch to below
ZFBC5   LDAA    #$28                     *FBC5: 86 28    ; Load $28 to AccA
        STAA    JMode                    *FBC7: 97 CA    ; Store A in mem
        CLRA                             *FBC9: 4F       ; Clear AccA
        CLRB                             *FBCA: 5F       ; Clear AccB
        STD     J0Data                   *FBCB: DD A4    ; Store D in mem
        STD     M00A8                    *FBCD: DD A8    ; Store D in mem
        STD     M009E                    *FBCF: DD 9E    ; Store D in mem
ZFBD1   JMP     ZF91B                    *FBD1: 7E F9 1B ; Jump to above
;
; IKBD command $20: Memory load
ZFBD4   LDAB    #$04                     *FBD4: C6 04    ; Set AccB to $04
        JSR     ZFCFE                    *FBD6: BD FC FE ; Subroutine
        BCC     ZFC12                    *FBD9: 24 37    ; No carry? Branch
        LDX     #MemPnt                  *FBDB: CE 00 EE ; Base addr. to X
        JSR     ZFD1E                    *FBDE: BD FD 1E ; Subroutine
        OIM     #$10,TRCSR               *FBE1: 72 10 11 ; Enable Rx-IRQ
        AIM     #$F7,TCSR                *FBE4: 71 F7 08 ; Disable OC-IRQ
        LDX     MemPnt                   *FBE7: DE EE    ; Load mem to X
        LDAA    MemCnt                   *FBE9: 96 F0    ; Load mem to A
        BEQ     ZFC0E                    *FBEB: 27 21    ; If zero, branch
ZFBED   CLR     >RxCnt                   *FBED: 7F 00 CC ; Clear mem byte
        LDAB    #$64                     *FBF0: C6 64    ; Set AccB to 100
ZFBF2   TIM     #$80,M00CB               *FBF2: 7B 80 CB ; Test mem bit 7
        BNE     ZFC01                    *FBF5: 26 0A    ; If set, branch
        LDAA    #$C8                     *FBF7: 86 C8    ; Set AccA to 200
ZFBF9   DECA                             *FBF9: 4A       ; This is a...
        BNE     ZFBF9                    *FBFA: 26 FD    ; ...delay loop
        DECB                             *FBFC: 5A       ; Decrease B
        BEQ     ZFC0E                    *FBFD: 27 0F    ; Branch if not 0
        BRA     ZFBF2                    *FBFF: 20 F1    ; Loop
ZFC01   AIM     #$7F,M00CB               *FC01: 71 7F CB ; Unset mem.bit 7
        LDAA    RxDat0                   *FC04: 96 CD    ; Load mem to AccA
        STAA    ,X                       *FC06: A7 00    ; Store A->mem(X)
        INX                              *FC08: 08       ; Increase X
        DEC     >MemCnt                  *FC09: 7A 00 F0 ; Decrease mem
        BNE     ZFBED                    *FC0C: 26 DF    ; Branch if not 0
ZFC0E   OIM     #$08,TCSR                *FC0E: 72 08 08 ; Enable OC-IRQ
        RTS                              *FC11: 39       ; Return
ZFC12   OIM     #$10,TRCSR               *FC12: 72 10 11 ; Enable Rx-IRQ
        RTS                              *FC15: 39       ; Return
;
; IKBD command $21: Memory read
ZFC16   LDAB    #$03                     *FC16: C6 03    ; Set AccB to $03
        JSR     ZFCFE                    *FC18: BD FC FE ; Subroutine
        BCC     ZFC37                    *FC1B: 24 1A    ; No carry? Branch
        LDX     #MemPnt                  *FC1D: CE 00 EE ; Base addr. to X
        JSR     ZFD1E                    *FC20: BD FD 1E ; Subroutine
        SEI                              *FC23: 0F       ; Disable IRQs
        LDAA    #$F6                     *FC24: 86 F6    ; Set AccA to $F6
        CLRB                             *FC26: 5F       ; Clear AccB
        JSR     ZFD34                    *FC27: BD FD 34 ; Subroutine
        LDAA    #$20                     *FC2A: 86 20    ; Set AccA to $20
        LDAB    #$06                     *FC2C: C6 06    ; Set AccB to $06
        LDX     MemPnt                   *FC2E: DE EE    ; Load X from mem
        JSR     ZFD34                    *FC30: BD FD 34 ; Subroutine
        CLI                              *FC33: 0E       ; Enable IRQs
        JMP     ZF91B                    *FC34: 7E F9 1B ; Jump to above
ZFC37   OIM     #$10,TRCSR               *FC37: 72 10 11 ; Enable RxIRQ
        RTS                              *FC3A: 39       ; Return
;
; IKBD command $22: Controller execute
ZFC3B   LDAB    #$03                     *FC3B: C6 03    ; Set AccB to $03
        JSR     ZFCFE                    *FC3D: BD FC FE ; Subroutine
        BCC     ZFC55                    *FC40: 24 13    ; No carry? Branch
        LDX     #MemPnt                  *FC42: CE 00 EE ; Base addr. to X
        JSR     ZFD1E                    *FC45: BD FD 1E ; Subroutine
        AIM     #$F7,TCSR                *FC48: 71 F7 08 ; Disable OC-IRQ
        LDX     MemPnt                   *FC4B: DE EE    ; Load X from mem
        JSR     ,X                       *FC4D: AD 00    ; Subrout. mem(X)
        OIM     #$08,TCSR                *FC4F: 72 08 08 ; Enable OC-IRQ
        JMP     ZF91B                    *FC52: 7E F9 1B ; Jump to above
ZFC55   OIM     #$10,TRCSR               *FC55: 72 10 11 ; Enable RxIRQ
        RTS                              *FC58: 39       ; Return
;
; IKBD command $87: Status inquiry - mouse button action
ZFC59   LDAA    #$07                     *FC59: 86 07    ; Set AccA to $07
        LDX     #MBActn                  *FC5B: CE 00 B4 ; Base addr. to X
        LDAB    #$02                     *FC5E: C6 02    ; Set AccB to $02
        BRA     ZFCD7                    *FC60: 20 75    ; Branch to below
;
; IKBD command $88/$89/$8A: Status inquiry - mouse mode
ZFC62   LDAA    MMode                    *FC62: 96 C9    ; Load mem to AccA
        ASLA                             *FC64: 48       ; Shift AccA left
        ASLA                             *FC65: 48       ; Shift AccA left
        BCS     ZFC71                    *FC66: 25 09    ; Branch if carry
        ASLA                             *FC68: 48       ; Shift AccA left
        BCS     ZFC7A                    *FC69: 25 0F    ; Branch if carry
        LDAA    #$08                     *FC6B: 86 08    ; Set AccA to $08
        LDAB    #$01                     *FC6D: C6 01    ; Set AccB to $01
        BRA     ZFCD7                    *FC6F: 20 66    ; Branch to below
ZFC71   LDAA    #$0A                     *FC71: 86 0A    ; Set AccA to $0A
        LDX     #MKCodDx                 *FC73: CE 00 AE ; Base addr. to X
        LDAB    #$03                     *FC76: C6 03    ; Set AccB to $03
        BRA     ZFCD7                    *FC78: 20 5D    ; Branch to below
ZFC7A   LDAA    #$09                     *FC7A: 86 09    ; Set AccA to $09
        LDX     #MAbMaxX                 *FC7C: CE 00 AA ; Base addr. to X
        LDAB    #$05                     *FC7F: C6 05    ; Set AccB to $05
        BRA     ZFCD7                    *FC81: 20 54    ; Branch to below
;
; IKBD command $8B: Status inquiry - mouse threshold
ZFC83   LDAA    #$0B                     *FC83: 86 0B    ; Set AccA to $0B
        LDX     #MEvThrX                 *FC85: CE 00 B0 ; Base addr. to X
        LDAB    #$03                     *FC88: C6 03    ; Set AccB to $03
        BRA     ZFCD7                    *FC8A: 20 4B    ; Branch to below
;
; IKBD command $8C: Status inquiry - mouse scale
ZFC8C   LDAA    #$0C                     *FC8C: 86 0C    ; Set AccA to $0C
        LDX     #MAbsScX                 *FC8E: CE 00 B2 ; Base addr. to X
        LDAB    #$03                     *FC91: C6 03    ; Set AccB to $03
        BRA     ZFCD7                    *FC93: 20 42    ; Branch to below
;
; IKBD command $8F/$90: Status inquiry - mouse vertical coordinates
ZFC95   LDAA    MMode                    *FC95: 96 C9    ; Load mem to AccA
        LSRA                             *FC97: 44       ; Shift A right
        BCS     ZFC9E                    *FC98: 25 04    ; Carry set? Bra.
        LDAA    #$10                     *FC9A: 86 10    ; Set AccA to $10
        BRA     ZFCD5                    *FC9C: 20 37    ; Branch to below
ZFC9E   LDAA    #$0F                     *FC9E: 86 0F    ; Set AccA to $0F
        BRA     ZFCD5                    *FCA0: 20 33    ; Branch to below
;
; IKBD command $92: Status inquiry - mouse enable/disable
ZFCA2   LDAA    MMode                    *FCA2: 96 C9    ; Load mem to AccA
        ASLA                             *FCA4: 48       ; Shift A left
        BCS     ZFCAB                    *FCA5: 25 04    ; Carry set? Bra.
        LDAA    #$12                     *FCA7: 86 12    ; Set AccA to $12
        BRA     ZFCD5                    *FCA9: 20 2A    ; Branch to below
ZFCAB   CLRA                             *FCAB: 4F       ; Clear AccA
        BRA     ZFCD5                    *FCAC: 20 27    ; Branch to below
;
; IKBD command $94/$95/$99: Status inquiry - Joystick mode
ZFCAE   LDAA    JMode                    *FCAE: 96 CA    ; Load mem to AccA
        LSRA                             *FCB0: 44       ; Shift A right
        LSRA                             *FCB1: 44       ; Shift A right
        LSRA                             *FCB2: 44       ; Shift A right
        BCS     ZFCBC                    *FCB3: 25 07    ; Branch if carry
        LSRA                             *FCB5: 44       ; Shift A right
        BCS     ZFCC5                    *FCB6: 25 0D    ; Branch if carry
        LDAA    #$15                     *FCB8: 86 15    ; Set AccA to $15
        BRA     ZFCD5                    *FCBA: 20 19    ; Branch to below
ZFCBC   LDAA    #$19                     *FCBC: 86 19    ; Set AccA to $19
        LDX     #JKCodRx                 *FCBE: CE 00 95 ; Base addr. to X
        LDAB    #$07                     *FCC1: C6 07    ; Set AccB to $07
        BRA     ZFCD7                    *FCC3: 20 12    ; Branch to below
ZFCC5   LDAA    #$14                     *FCC5: 86 14    ; Set AccA to $14
        BRA     ZFCD5                    *FCC7: 20 0C    ; Branch to below
;
; IKBD command $9A: Status inquiry - Joystick enable/disable
        TIM     #$20,JMode               *FCC9: 7B 20 CA ; Test mem bit 5
        BNE     ZFCD2                    *FCCC: 26 04    ; Branch if set
        LDAA    #$1A                     *FCCE: 86 1A    ; Set AccA to $1A
        BRA     ZFCD5                    *FCD0: 20 03    ; Branch to below
ZFCD2   CLRA                             *FCD2: 4F       ; Clear AccA
        BRA     ZFCD5                    *FCD3: 20 00    ; Branch to below
;
; Status inquiries that need to set AccB to $01 end here
ZFCD5   LDAB    #$01                     *FCD5: C6 01    ; Set AccB to $01
; Status inquiries that do not need to preset AccB end here
ZFCD7   STAA    M00C6                    *FCD7: 97 C6    ; Store A in mem
        STAB    M00C5                    *FCD9: D7 C5    ; Store B in mem
        SEI                              *FCDB: 0F       ; Disable IRQs
        PSHX                             *FCDC: 3C       ; Push X to Stack
        LDAA    #$F6                     *FCDD: 86 F6    ; Set AccA to $F6
        CLRB                             *FCDF: 5F       ; Clear AccB
        JSR     ZFD34                    *FCE0: BD FD 34 ; Subroutine
        PULX                             *FCE3: 38       ; Get X from stack
        LDAA    M00C6                    *FCE4: 96 C6    ; Load mem to AccA
        LDAB    M00C5                    *FCE6: D6 C5    ; Load mem to AccB
        DECB                             *FCE8: 5A       ; Decrease B
ZFCE9   JSR     ZFD34                    *FCE9: BD FD 34 ; Subroutine
        LDAB    M00C5                    *FCEC: D6 C5    ; Load mem to AccB
        INCB                             *FCEE: 5C       ; Increase AccB
        CMPB    #$08                     *FCEF: C1 08    ; Check B for $08
        BEQ     ZFCFA                    *FCF1: 27 07    ; Branch if equal
        STAB    M00C5                    *FCF3: D7 C5    ; Store AccB here
        LDD     #$0000                   *FCF5: CC 00 00 ; Reset D to $0000
        BRA     ZFCE9                    *FCF8: 20 EF    ; Branch to below
ZFCFA   CLI                              *FCFA: 0E       ; Enable IRQs
        JMP     ZF929                    *FCFB: 7E F9 29 ; Jump to above
;
; Subroutine to check number of serial received bytes against AccB
; Returns with carry clear if more bytes than AccB have been received
ZFCFE   AIM     #$EF,TRCSR               *FCFE: 71 EF 11 ; Disable RxIE
        LDAA    M00CB                    *FD01: 96 CB    ; Load mem to AccA
        BITA    #$40                     *FD03: 85 40    ; Test A bit 5
        BNE     ZFD16                    *FD05: 26 0F    ; If set, branch
        CMPB    RxCnt                    *FD07: D1 CC    ; Compare B to mem
        BCS     ZFD16                    *FD09: 25 0B    ; If lower, branch
        BEQ     ZFD16                    *FD0B: 27 09    ; If equal, branch
        SUBB    RxCnt                    *FD0D: D0 CC    ; Sub mem from B
        ORAB    M00CB                    *FD0F: DA CB    ; OR B with mem
        STAB    M00CB                    *FD11: D7 CB    ; Store B there
        CLC                              *FD13: 0C       ; Clear carry
        BRA     ZFD1D                    *FD14: 20 07    ; Branch to below
ZFD16   ANDA    #$18                     *FD16: 84 18    ; AND A with $18
        DECB                             *FD18: 5A       ; Decrease AccB
        ABA                              *FD19: 1B       ; Add AccB to AccA
        STAA    M00CB                    *FD1A: 97 CB    ; Store AccA there
        SEC                              *FD1C: 0D       ; Set Carry
ZFD1D   RTS                              *FD1D: 39       ; Return
;
; Subroutine to copy Rx-Data from byte 1 on to memory pointed to by X
ZFD1E   CLRB                             *FD1E: 5F       ; Clear AccB
ZFD1F   PSHX                             *FD1F: 3C       ; Push X to stack
        LDX     #RxDat0                  *FD20: CE 00 CD ; Base addr. to X
        ABX                              *FD23: 3A       ; Add AccB to X
        LDAA    $01,X                    *FD24: A6 01    ; Read (mem+X)->A
        PULX                             *FD26: 38       ; Get X from stack
        STAA    ,X                       *FD27: A7 00    ; Put A to mem(X)
        INX                              *FD29: 08       ; Increase X
        INCB                             *FD2A: 5C       ; Increase AccB
        DEC     >M00CB                   *FD2B: 7A 00 CB ; Decrease mem
        TIM     #$07,M00CB               *FD2E: 7B 07 CB ; Test mem for $07
        BNE     ZFD1F                    *FD31: 26 EC    ; Branch if not eq
        RTS                              *FD33: 39       ; Return
;
; Subroutine to generate serial response
;     AccA = Return Code,
;     AccB = Length of response
;        X = Base pointer for the data
;
;    If M00D7 bit 7 is set, unsets the bit and calls serial transmit,
;    if M00D7 bit 7 is clear, it sets the carry bit and returns
ZFD34   TIM     #$10,M00CB               *FD34: 7B 10 CB ; Check mem bit 4
        BNE     ZFD67                    *FD37: 26 2E    ; If set, branch
        CMPB    M00D7                    *FD39: D1 D7    ; Check B <-> mem
        BCC     ZFD67                    *FD3B: 24 2A    ; If lower, branch
ZFD3D   PSHX                             *FD3D: 3C       ; Push X to stack
        XGDX                             *FD3E: 18       ; Exchange D <-> X
        CLRA                             *FD3F: 4F       ; Clear AccA
        LDAB    TxNo                     *FD40: D6 D5    ; Load mem to AccB
        XGDX                             *FD42: 18       ; Exchange D <-> X
        STAA    TxDat0,X                 *FD43: A7 D9    ; Store A->(mem+X)
        LDAA    TxNo                     *FD45: 96 D5    ; Load mem to AccA
        INCA                             *FD47: 4C       ; Increase AccA
        CMPA    #$15                     *FD48: 81 15    ; Check A for $15
        BNE     ZFD4D                    *FD4A: 26 01    ; No match? Branch
        CLRA                             *FD4C: 4F       ; Matched? Clear A
ZFD4D   STAA    TxNo                     *FD4D: 97 D5    ; Store A in mem
        DEC     >M00D7                   *FD4F: 7A 00 D7 ; Decrease mem
        PULX                             *FD52: 38       ; Get X from stack
        TSTB                             *FD53: 5D       ; Test AccB
        BEQ     ZFD5C                    *FD54: 27 06    ; Branch if zero
        LDAA    ,X                       *FD56: A6 00    ; Load mem(X) to A
        INX                              *FD58: 08       ; Increase X
        DECB                             *FD59: 5A       ; Decrease B
        BRA     ZFD3D                    *FD5A: 20 E1    ; Loop
ZFD5C   LDAA    M00D7                    *FD5C: 96 D7    ; Read mem to AccA
        BPL     ZFD66                    *FD5E: 2A 06    ; If pos., branch
        AIM     #$7F,M00D7               *FD60: 71 7F D7 ; Clear mem bit 7
        JSR     ZFD68                    *FD63: BD FD 68 ; Subroutine
ZFD66   SEC                              *FD66: 0D       ; Set carry bit
ZFD67   RTS                              *FD67: 39       ; Return
;
; This seems to be the serial transmit (sub)routine
ZFD68   LDAA    TRCSR                    *FD68: 96 11    ; Get Serial-reg.
        BITA    #$20                     *FD6A: 85 20    ; Check Tx empty
        BEQ     ZFD9C                    *FD6C: 27 2E    ; If clear, branch
        LDAA    TxCnt                    *FD6E: 96 D6    ; Load mem to AccA
        LDAB    M00CB                    *FD70: D6 CB    ; Load mem to AccB
        BITB    #$08                     *FD72: C5 08    ; Check B bit 3
        BEQ     ZFD7A                    *FD74: 27 04    ; If clear, branch
        CMPA    TxLim                    *FD76: 91 D8    ; Compare A<->mem
        BEQ     ZFD9C                    *FD78: 27 22    ; Branch if equal
ZFD7A   LDX     #TxDat0                  *FD7A: CE 00 D9 ; Base addr. to X
        LDAB    TxCnt                    *FD7D: D6 D6    ; Read mem to AccB
        ABX                              *FD7F: 3A       ; Add AccB to X
        LDAB    ,X                       *FD80: E6 00    ; Load mem(X) to B
        STAB    TXB                      *FD82: D7 13    ; Write to Tx-Buf.
        OIM     #$04,TRCSR               *FD84: 72 04 11 ; Enable TxIRQ
        INCA                             *FD87: 4C       ; Increase AccA
        CMPA    #$15                     *FD88: 81 15    ; Check A for $15
        BNE     ZFD8D                    *FD8A: 26 01    ; No match? Branch
        CLRA                             *FD8C: 4F       ; Clear AccA
ZFD8D   STAA    TxCnt                    *FD8D: 97 D6    ; Store A in mem
        LDAA    M00D7                    *FD8F: 96 D7    ; Load mem to AccA
        ANDA    #$7F                     *FD91: 84 7F    ; Mask out A bit 7
        INCA                             *FD93: 4C       ; Increase AccA
        CMPA    #$15                     *FD94: 81 15    ; Compare A to $15
        BNE     ZFD9A                    *FD96: 26 02    ; No match? Branch
        ORAA    #$80                     *FD98: 8A 80    ; Set Bit 7 of A
ZFD9A   STAA    M00D7                    *FD9A: 97 D7    ; Store A in mem
ZFD9C   RTS                              *FD9C: 39       ; Return

; 
; Interrupt service routine: Output Compare (occurs once every millisec.)
;   First, manage the 1ms counter and reload output compare register
hdlr_SWI2 
        LDAA    TCSR                     *FD9D: 96 08    ; Get Timer-reg.
        BITA    #$40                     *FD9F: 85 40    ; Check OCF-Bit
        BNE     ZFDA6                    *FDA1: 26 03    ; If set, branch
        JMP     ZFECF                    *FDA3: 7E FE CF ; Jump to RTI
ZFDA6   LDD     FRCH                     *FDA6: DC 09    ; Get Counter to D
        ADDB    #$13                     *FDA8: CB 13    ; Add $13 to AccB
        CMPB    OCRL                     *FDAA: D1 0C    ; Check B<->OCRLow
        BNE     ZFDAF                    *FDAC: 26 01    ; No match? Branch
        NOP                              *FDAE: 01       ; Waste cycles
ZFDAF   LDD     OCRH                     *FDAF: DC 0B    ; Read OCR to D
        ADDD    #$03E8                   *FDB1: C3 03 E8 ; Add 1000 to D 
        STD     OCRH                     *FDB4: DD 0B    ; Store as new OCR
        LDAA    TodMon                   *FDB6: 96 83    ; Fetch mem to A
        BNE     ZFDBD                    *FDB8: 26 03    ; Not zero? Branch
ZFDBA   JMP     ZFE29                    *FDBA: 7E FE 29 ; Jump to below
ZFDBD   LDX     Cnt1ms                   *FDBD: DE 80    ; Load mem to X
        DEX                              *FDBF: 09       ; Decrease X
        STX     Cnt1ms                   *FDC0: DF 80    ; Write X to mem
        BNE     ZFDBA                    *FDC2: 26 F6    ; Branch if not 0
        LDX     #$03E8                   *FDC4: CE 03 E8 ; Set X to 1000
        STX     Cnt1ms                   *FDC7: DF 80    ; Store X in mem
;
; Now manage time-of-day. First handle seconds, minutes and hours
        LDX     #$0006                   *FDC9: CE 00 06 ; Set X to 6
        LDAB    #$60                     *FDCC: C6 60    ; Set AccB to $60
ZFDCE   DEX                              *FDCE: 09       ; Decrease X
        LDAA    TodYr,X                  *FDCF: A6 82    ; Load (mem+X)->A
        ADDA    #$01                     *FDD1: 8B 01    ; Add 1 to AccA
        DAA                              *FDD3: 19       ; Decimal adjust
        CPX     #$0000                   *FDD4: 8C 00 00 ; Is X zero?
        BEQ     ZFE27                    *FDD7: 27 4E    ; If so, branch
        CBA                              *FDD9: 11       ; Compare A and B
        BNE     ZFE27                    *FDDA: 26 4B    ; Branch if not eq
        CLRA                             *FDDC: 4F       ; Clear AccA
        STAA    TodYr,X                  *FDDD: A7 82    ; Store A->(mem+X)
        CPX     #$0005                   *FDDF: 8C 00 05 ; Compare X to 5
        BEQ     ZFDCE                    *FDE2: 27 EA    ; Branch if equal
        CPX     #$0004                   *FDE4: 8C 00 04 ; Compare X to 4
        BNE     ZFDED                    *FDE7: 26 04    ; Branch if not eq
        LDAB    #$24                     *FDE9: C6 24    ; Set AccB to $24
        BRA     ZFDCE                    *FDEB: 20 E1    ; Branch to above
;
; Now handle time-of-day day, month and year
ZFDED   CPX     #$0003                   *FDED: 8C 00 03 ; Compare X to 3
        BNE     ZFE1E                    *FDF0: 26 2C    ; Branch if not eq
        LDAB    TodMon                   *FDF2: D6 83    ; Load month to B
        CMPB    #$02                     *FDF4: C1 02    ; Is it February?
        BNE     ZFE10                    *FDF6: 26 18    ; Branch if not eq
        LDAB    #$29                     *FDF8: C6 29    ; Set AccB to $29
        LDAA    TodDay                   *FDFA: 96 84    ; Load mem to AccA
        CMPA    #$28                     *FDFC: 81 28    ; Compare A to $28
        BCS     ZFDCE                    *FDFE: 25 CE    ; If lower, branch
        LDAA    TodYr                    *FE00: 96 82    ; Load mem to AccA
        BITA    #$10                     *FE02: 85 10    ; Test A bit 4
        BEQ     ZFE08                    *FE04: 27 02    ; If clear, branch
        ADDA    #$0A                     *FE06: 8B 0A    ; Add 10 to AccA
ZFE08   ANDA    #$03                     *FE08: 84 03    ; 2 low bits of A
        BNE     ZFDCE                    *FE0A: 26 C2    ; If not 0, branch
        LDAB    #$30                     *FE0C: C6 30    ; Set AccB to $30
        BRA     ZFDCE                    *FE0E: 20 BE    ; Branch to above
ZFE10   LDX     #MFED0                   *FE10: CE FE D0 ; Base addr. to X
        LDAB    TodMon                   *FE13: D6 83    ; Load mem to AccB
        DECB                             *FE15: 5A       ; Decrease B
        ABX                              *FE16: 3A       ; Add AccB to X
        LDAB    ,X                       *FE17: E6 00    ; Read mem(X) to B
        LDX     #$0003                   *FE19: CE 00 03 ; Set X to 3
        BRA     ZFDCE                    *FE1C: 20 B0    ; Branch to above
ZFE1E   LDAA    #$01                     *FE1E: 86 01    ; Set AccA to 1
        STAA    $TodYr,X                 *FE20: A7 82    ; Store A->(mem+X)
        LDAB    #$13                     *FE22: C6 13    ; Set AccB to $13
        JMP     ZFDCE                    *FE24: 7E FD CE ; Jump to above
ZFE27   STAA    TodYr,X                  *FE27: A7 82    ; Store A->(mem+X)
;
; Now handle the reset detection issued by a 200ms low on the Rx-line
ZFE29   LDAA    RxErr                    *FE29: 96 D4    ; Load mem to AccA
        BEQ     ZFE4E                    *FE2B: 27 21    ; If zero, branch
        CMPA    #$CD                     *FE2D: 81 CD    ; Check A for 205
        BNE     ZFE3E                    *FE2F: 26 0D    ; Branch if not eq
        LDS     #$00FF                   *FE31: 8E 00 FF ; Reset stack
        LDX     #ZF00B                   *FE34: CE F0 0B ; Soft entry to X
        PSHX                             *FE37: 3C       ; Push X to stack
        LDS     #$00F8                   *FE38: 8E 00 F8 ; Set stack to $F8
        JMP     ZFECF                    *FE3B: 7E FE CF ; Do a soft reset!
; 
ZFE3E   TIM     #$01,TRCSR               *FE3E: 7B 01 11 ; Test for wake-up
        BNE     ZFE4B                    *FE41: 26 08    ; If set, branch
        CLRA                             *FE43: 4F       ; Clear AccA
        AIM     #$EF,M00CB               *FE44: 71 EF CB ; AND mem with $EF
        OIM     #$04,TRCSR               *FE47: 72 04 11 ; Enable TxIRQ
; The following 2 bytes can be interpreted differently:
        TST     $4C,X                    *FE4A: 6D 4C    ; Bogus mem test
; Or, in case $FE4B is being branched to from above:
        FCB     $6D                      *FE4A: 6D       ; Data '.'
        INCA                             *FE4B: 4C       ; Increase AccA
;
        STAA    RxErr                    *FE4C: 97 D4    ; Store A in mem
ZFE4E   LDAB    JMode                    *FE4E: D6 CA    ; Load B from mem
        LDAA    MMode                    *FE50: 96 C9    ; Load A from mem
        BITA    #$02                     *FE52: 85 02    ; Test A bit 1
        BNE     ZFE5F                    *FE54: 26 09    ; If set, branch
        BITB    #$20                     *FE56: C5 20    ; Test B bit 5
        BNE     ZFE67                    *FE58: 26 0D    ; If set, branch
        TSTA                             *FE5A: 4D       ; Test AccA
        BMI     ZFE6E                    *FE5B: 2B 11    ; If neg., branch
        BRA     ZFEC5                    *FE5D: 20 66    ; Branch to below
ZFE5F   BITB    #$20                     *FE5F: C5 20    ; Test B bit 5
        BEQ     ZFEC5                    *FE61: 27 62    ; If clear, branch
        BITB    #$01                     *FE63: C5 01    ; Test B bit 1
        BCS     ZFECF                    *FE65: 25 68    ; Branch if carry
ZFE67   LDAA    M009E                    *FE67: 96 9E    ; Load mem to AccA
        BEQ     ZFE6E                    *FE69: 27 03    ; If zero, branch
        INCA                             *FE6B: 4C       ; Increase AccA
        STAA    M009E                    *FE6C: 97 9E    ; Store A again
ZFE6E   LDAA    M009D                    *FE6E: 96 9D    ; Load mem to AccA
        BEQ     ZFE75                    *FE70: 27 03    ; If zero, branch
        INCA                             *FE72: 4C       ; Increase AccA
        STAA    M009D                    *FE73: 97 9D    ; Store A again
ZFE75   BITB    #$20                     *FE75: C5 20    ; Test B bit 5
        BEQ     ZFEC5                    *FE77: 27 4C    ; If clear, branch
        BITB    #$04                     *FE79: C5 04    ; Test B bit 2
        BEQ     ZFEA8                    *FE7B: 27 2B    ; If clear, branch
        LDX     #$0000                   *FE7D: CE 00 00 ; Reset X to $0000
ZFE80   LDAA    J0KCodC,X                *FE80: A6 A2    ; Read (mem+X)->A
        BEQ     ZFE8C                    *FE82: 27 08    ; If zero, branch
        DECA                             *FE84: 4A       ; Decrease AccA
        STAA    J0KCodC,X                *FE85: A7 A2    ; Store A again
        DEX                              *FE87: 09       ; Decrease X
        BEQ     ZFEC5                    *FE88: 27 3B    ; If zero, branch
        BRA     ZFEA3                    *FE8A: 20 17    ; Branch to below
ZFE8C   LDAA    #$64                     *FE8C: 86 64    ; Set AccA to #100
        STAA    J0KCodC,X                *FE8E: A7 A2    ; Store A->(mem+X)
ZFE90   INX                              *FE90: 08       ; Increase X...
        INX                              *FE91: 08       ; ...twice
        LDAA    J0KCodC,X                *FE92: A6 A2    ; Load (mem+X)->A
        BEQ     ZFE99                    *FE94: 27 03    ; If zero, branch
        DECA                             *FE96: 4A       ; Else, decrease A
        STAA    J0KCodC,X                *FE97: A7 A2    ; and store AccA
ZFE99   CPX     #$0006                   *FE99: 8C 00 06 ; Compare X to 6
        BCS     ZFE90                    *FE9C: 25 F2    ; If lower, branch
        CPX     #$0007                   *FE9E: 8C 00 07 ; Compare X to 7
        BEQ     ZFEC5                    *FEA1: 27 22    ; Branch if equal
ZFEA3   LDX     #$0002                   *FEA3: CE 00 01 ; Set X to $0002
        BRA     ZFE80                    *FEA6: 20 D8    ; Branch to above
ZFEA8   BITB    #$02                     *FEA8: C5 02    ; Test B bit 1
        BEQ     ZFEC5                    *FEAA: 27 19    ; If clear, branch
        TIM     #$08,M00CB               *FEAC: 7B 08 CB ; Test mem bit 3
        BNE     ZFECF                    *FEAF: 26 1E    ; If set, branch
        LDAA    M00A6                    *FEB1: 96 A6    ; Load mem to AccA
        BEQ     ZFEB8                    *FEB3: 27 03    ; If zero, branch
        DECA                             *FEB5: 4A       ; Decrease AccA
        BRA     ZFEC1                    *FEB6: 20 09    ; Branch to below
ZFEB8   LDAA    #$0A                     *FEB8: 86 0A    ; Set AccA to #10
        LDAB    JMonRC                   *FEBA: D6 A7    ; Load mem to AccB
        BEQ     ZFEC1                    *FEBC: 27 03    ; Branch if zero
        DECB                             *FEBE: 5A       ; Else, decrease B
        STAB    JMonRC                   *FEBF: D7 A7    ; Store B in mem
ZFEC1   STAA    M00A6                    *FEC1: 97 A6    ; Store A in mem
        BRA     ZFECF                    *FEC3: 20 0A    ; Branch to RTI
ZFEC5   LDAA    M0089                    *FEC5: 96 89    ; Load mem to AccA
        BMI     ZFECC                    *FEC7: 2B 03    ; If neg., branch
        JMP     ZF1B7                    *FEC9: 7E F1 B7 ; Jump to above
ZFECC   EIM     #$80,M0089               *FECC: 75 80 89 ; XOR bit 7 in mem
ZFECF   RTI                              *FECF: 3B       ; Return from ISR
;
; This table contains (maximum) duration per month in days plus one
MFED0   FCB     $32                      *FED0: 32       ; January
        FCB     $29                      *FED1: 29       ; February
        FCB     $32                      *FED2: 32       ; March
        FCB     $31                      *FED3: 31       ; April
        FCB     $32                      *FED4: 32       ; May
        FCB     $31                      *FED5: 31       ; June
        FCB     $32                      *FED6: 32       ; July
        FCB     $32                      *FED7: 32       ; August
        FCB     $31                      *FED8: 31       ; September
        FCB     $00                      *FED9: 00       ; Not in BCD
        FCB     $00                      *FEDA: 00       ; Not in BCD
        FCB     $00                      *FEDB: 00       ; Not in BCD
        FCB     $00                      *FEDC: 00       ; Not in BCD
        FCB     $00                      *FEDD: 00       ; Not in BCD
        FCB     $00                      *FEDE: 00       ; Not in BCD
        FCB     $32                      *FEDF: 32       ; October
        FCB     $31                      *FEE0: 31       ; November
        FCB     $32                      *FEE1: 32       ; December
;
; Interrupt Service Routine (formerly hdlr_DIV0): Serial I/O
hdlr_SWI4
        LDAA    TRCSR                    *FEE2: 96 11    ; Read Serial-Reg.
        BITA    #$40                     *FEE4: 85 40    ; Test ORFE-Bit
        BNE     ZFEF4                    *FEE6: 26 0C    ; If set, branch
        BITA    #$80                     *FEE8: 85 80    ; Test RDRF-Bit
        BNE     ZFEF1                    *FEEA: 26 05    ; If set, branch
        BITA    #$20                     *FEEC: 85 20    ; Test TDRE-Bit
        BNE     ZFEF7                    *FEEE: 26 07    ; If set, branch
        RTI                              *FEF0: 3B       ; Return from ISR
ZFEF1   BSR     ZFF04                    *FEF1: 8D 11    ; Subroutine
        RTI                              *FEF3: 3B       ; Return from ISR
;
; Serial overrun/framing error handling via subroutine
ZFEF4   BSR     ZFF40                    *FEF4: 8D 4A    ; Subroutine
        RTI                              *FEF6: 3B       ; Return from ISR
;
; Transmit Data Register Empty handling below
ZFEF7   LDAA    M00D7                    *FEF7: 96 D7    ; Read mem to AccA
        BPL     ZFF00                    *FEF9: 2A 05    ; If pos., branch
        AIM     #$FB,TRCSR               *FEFB: 71 FB 11 ; Disable TxIRQ
        BRA     ZFF03                    *FEFE: 20 03    ; Skip next instr.
ZFF00   JSR     ZFD68                    *FF00: BD FD 68 ; Subroutine
ZFF03   RTI                              *FF03: 3B       ; Return from ISR
;
; Receive Data Buffer Full handling below
ZFF04   LDAB    RxCnt                    *FF04: D6 CC    ; Load mem to AccB
        LDAA    RXB                      *FF06: 96 12    ; Load RxBuf to A
        BNE     ZFF0D                    *FF08: 26 03    ; If not 0, branch
        TSTB                             *FF0A: 5D       ; Test AccB
        BEQ     ZFF3F                    *FF0B: 27 32    ; If zero, return
ZFF0D   CMPB    #$07                     *FF0D: C1 07    ; Check B for $07
        BEQ     ZFF3F                    *FF0F: 27 2E    ; Return if equal
        LDAA    M00CB                    *FF11: 96 CB    ; Load mem to AccA
        BITA    #$20                     *FF13: 85 20    ; Test A bit 5
        BNE     ZFF33                    *FF15: 26 1C    ; If set, branch
        LDX     #RxDat0                  *FF17: CE 00 CD ; Base addr. to X
        ABX                              *FF1A: 3A       ; Add AccB to X
        LDAB    RXB                      *FF1B: D6 12    ; Load RxBuf to B
        STAB    ,X                       *FF1D: E7 00    ; Store B->mem(X)
        INC     >RxCnt                   *FF1F: 7C 00 CC ; Increase mem
        BITA    #$07                     *FF22: 85 07    ; Test A bit 3
        BEQ     ZFF2D                    *FF24: 27 07    ; If clear, branch
        DECA                             *FF26: 4A       ; Decrease AccA
        BITA    #$07                     *FF27: 85 07    ; Test A bit 2,1,0
        BNE     ZFF2F                    *FF29: 26 04    ; Branch if set
        ORAA    #$40                     *FF2B: 8A 40    ; Set Bit 6 of A
ZFF2D   ORAA    #$80                     *FF2D: 8A 80    ; Set Bit 7 of a
ZFF2F   STAA    M00CB                    *FF2F: 97 CB    ; Store A in mem
        BRA     ZFF3F                    *FF31: 20 0C    ; Return
ZFF33   DECA                             *FF33: 4A       ; Decrease AccA
        BITA    #$07                     *FF34: 85 07    ; Test A bit 2,1,0
        BNE     ZFF2F                    *FF36: 26 F7    ; If set, branch
        ANDA    #$18                     *FF38: 84 18    ; AND A with $18
        STAA    M00CB                    *FF3A: 97 CB    ; Store A in mem
        CLRA                             *FF3C: 4F       ; Clear AccA
        STAA    RxCnt                    *FF3D: 97 CC    ; Store A in mem
ZFF3F   RTS                              *FF3F: 39       ; Return
;
; Covering overrun or framing errors here
ZFF40   LDAB    RXB                      *FF40: D6 12    ; Load RxBuf to B
        OIM     #$01,TRCSR               *FF42: 72 01 11 ; Enable Wake-Up
        LDAA    #$20                     *FF45: 86 20    ; Set AccA to #32
ZFF47   DECA                             *FF47: 4A       ; This is just...
        BNE     ZFF47                    *FF48: 26 FD    ; ...a wait loop
        TIM     #$01,TRCSR               *FF4A: 7B 01 11 ; Check WU-Bit
        BEQ     ZFF58                    *FF4D: 27 09    ; If clear, branch
        INC     >RxErr                   *FF4F: 7C 00 D4 ; Increase mem
        OIM     #$10,M00CB               *FF52: 72 10 CB ; OR mem with $10
        AIM     #$FB,TRCSR               *FF55: 71 FB 11 ; Disable TxIRQ
ZFF58   LDAA    M00CB                    *FF58: 96 CB    ; Load mem to AccA
        LDAB    RxCnt                    *FF5A: D6 CC    ; Load mem to AccB
        BEQ     ZFF63                    *FF5C: 27 05    ; Branch if zero
        DECA                             *FF5E: 4A       ; Decrease AccA
        BITA    #$07                     *FF5F: 85 07    ; Test A bit 2,1,0
        BNE     ZFF69                    *FF61: 26 06    ; If set, branch
ZFF63   ANDA    #$08                     *FF63: 84 08    ; AND A with $08
        CLRB                             *FF65: 5F       ; Clear AccB
        STAB    RxCnt                    *FF66: D7 CC    ; Store B there
;
; Again, this allows dual interpretation, depending on from where it is
; being entered: Either linearly or from the branch at $FF61:
        TST     $8A20                    *FF68: 7D 8A 20 ; Bogus mem test
; or
        FCB     $7D                      *FF68: 7D       ; Data '}'
ZFF69   ORAA    #$20                     *FF69: 8A 20    ; OR A with $20
;        
        STAA    M00CB                    *FF6B: 97 CB    ; Store A in mem
        RTS                              *FF6D: 39       ; Return
;
; Checksum correction byte
        FCB     $A6                      *FF6E: A6       ; Data '.'
;
        FCB     $FF                      *FF6F: FF       ; Data '.'
        FCB     $00                      *FF70: 00       ; Data '.'
        FCB     $FF                      *FF71: FF       ; Data '.'
        FCB     $00                      *FF72: 00       ; Data '.'
        FCB     $FF                      *FF73: FF       ; Data '.'
        FCB     $00                      *FF74: 00       ; Data '.'
        FCB     $FF                      *FF75: FF       ; Data '.'
        FCB     $00                      *FF76: 00       ; Data '.'
        FCB     $FF                      *FF77: FF       ; Data '.'
        FCB     $00                      *FF78: 00       ; Data '.'
        FCB     $FF                      *FF79: FF       ; Data '.'
        FCB     $00                      *FF7A: 00       ; Data '.'
        FCB     $FF                      *FF7B: FF       ; Data '.'
        FCB     $00                      *FF7C: 00       ; Data'.'
        FCB     $FF                      *FF7D: FF       ; Data '.'
        FCB     $00                      *FF7E: 00       ; Data '.'
        FCB     $FF                      *FF7F: FF       ; Data '.'
        FCB     $00                      *FF80: 00       ; Data '.'
        FCB     $FF                      *FF81: FF       ; Data '.'
        FCB     $00                      *FF82: 00       ; Data '.'
        FCB     $FF                      *FF83: FF       ; Data '.'
        FCB     $00                      *FF84: 00       ; Data '.'
        FCB     $FF                      *FF85: FF       ; Data '.'
        FCB     $00                      *FF86: 00       ; Data '.'
        FCB     $FF                      *FF87: FF       ; Data '.'
        FCB     $00                      *FF88: 00       ; Data '.'
        FCB     $FF                      *FF89: FF       ; Data '.'
        FCB     $00                      *FF8A: 00       ; Data '.'
        FCB     $FF                      *FF8B: FF       ; Data '.'
        FCB     $00                      *FF8C: 00       ; Data '.'
        FCB     $FF                      *FF8D: FF       ; Data '.'
        FCB     $00                      *FF8E: 00       ; Data '.'
        FCB     $FF                      *FF8F: FF       ; Data '.'
        FCB     $00                      *FF90: 00       ; Data '.'
        FCB     $FF                      *FF91: FF       ; Data '.'
        FCB     $00                      *FF92: 00       ; Data '.'
        FCB     $FF                      *FF93: FF       ; Data '.'
        FCB     $00                      *FF94: 00       ; Data '.'
        FCB     $FF                      *FF95: FF       ; Data '.'
        FCB     $00                      *FF96: 00       ; Data '.'
        FCB     $01                      *FF97: F1       ; Data '.'
        FCB     $14                      *FF98: 14       ; Data '.'
        FCB     $00                      *FF99: 00       ; Data '.'
        FCB     $01                      *FF9A: 01       ; Data '.'
        FCB     $46                      *FF9B: 46       ; Data 'F'
        FCB     $00                      *FF9C: 00       ; Data '.'
        FCB     $FF                      *FF9D: FF       ; Data '.'
        FCB     $F1                      *FF9E: F1       ; Data '.'
        FCB     $14                      *FF9F: 14       ; Data '.'
        FCB     $00                      *FFA0: 00       ; Data '.'
        FCB     $01                      *FFA1: 01       ; Data '.'
        FCB     $46                      *FFA2: 46       ; Data 'F'
        FCB     $7E                      *FFA3: 73       ; Data '-'
        FCB     $0A                      *FFA4: 0A       ; Data '.'
        FCB     $FF                      *FFA5: FF       ; Data '.'
        FCB     $00                      *FFA6: 00       ; Data '.'
        FCB     $FF                      *FFA7: FF       ; Data '.'
        FCB     $00                      *FFA8: 00       ; Data '.'
        FCB     $FF                      *FFA9: FF       ; Data '.'
        FCB     $00                      *FFAA: 00       ; Data '.'
        FCB     $FF                      *FFAB: FF       ; Data '.'
        FCB     $F1                      *FFAC: F1       ; Data '.'
        FCB     $14                      *FFAD: 14       ; Data '.'
        FCB     $00                      *FFAE: 00       ; Data '.'
        FCB     $01                      *FFAF: 01       ; Data '.'
        FCB     $31                      *FFB0: 31       ; Data '1'
        FCB     $00                      *FFB1: 00       ; Data '.'
        FCB     $FF                      *FFB2: FF       ; Data '.'
        FCB     $F1                      *FFB3: F1       ; Data '.'
        FCB     $14                      *FFB4: 14       ; Data '.'
        FCB     $00                      *FFB5: 00       ; Data '.'
        FCB     $01                      *FFB6: 01       ; Data '.'
        FCB     $31                      *FFB7: 31       ; Data '1'
        FCB     $7E                      *FFB8: 7E       ; Data '-'
        FCB     $0A                      *FFB9: 0A       ; Data '.'
        FCB     $00                      *FFBA: 00       ; Data '.'
        FCB     $FF                      *FFBB: FF       ; Data '.'
        FCB     $00                      *FFBC: 00       ; Data '.'
        FCB     $FF                      *FFBD: FF       ; Data '.'
        FCB     $00                      *FFBE: 00       ; Data '.'
        FCB     $FF                      *FFBF: FF       ; Data '.'
        FCB     $00                      *FFC0: 00       ; Data '.'
        FCB     $F1                      *FFC1: F1       ; Data '.'
        FCB     $14                      *FFC2: 14       ; Data '.'
        FCB     $00                      *FFC3: 00       ; Data '.'
        FCB     $01                      *FFC4: 01       ; Data '.'
        FCB     $1C                      *FFC5: 1C       ; Data '.'
        FCB     $00                      *FFC6: 00       ; Data '.'
        FCB     $FF                      *FFC7: FF       ; Data '.'
        FCB     $F1                      *FFC8: F1       ; Data '.'
        FCB     $14                      *FFC9: 14       ; Data '.'
        FCB     $00                      *FFCA: 00       ; Data '.'
        FCB     $01                      *FFCB: 01       ; Data '.'
        FCB     $1C                      *FFCC: 1C       ; Data '.'
        FCB     $7E                      *FFCD: 7E       ; Data '-'
        FCB     $0A                      *FFCE: 0A       ; Data '.'
        FCB     $FE                      *FFCF: FE       ; Data '.'
        FCB     $00                      *FFD0: 00       ; Data '.'
        FCB     $DF                      *FFD1: DF       ; Data '.'
        FCB     $00                      *FFD2: 00       ; Data '.'
        FCB     $FF                      *FFD3: FF       ; Data '.'
        FCB     $00                      *FFD4: 00       ; Data '.'
        FCB     $FF                      *FFD5: FF       ; Data '.'
        FCB     $F1                      *FFD6: F1       ; Data '.'
        FCB     $1C                      *FFD7: 1C       ; Data '.'
        FCB     $00                      *FFD8: 00       ; Data '.'
        FCB     $00                      *FFD9: 00       ; Data '.'
        FCB     $FF                      *FFDA: FF       ; Data '.'
        FCB     $01                      *FFDB: 01       ; Data '.'
        FCB     $02                      *FFDC: 02       ; Data '.'
        FCB     $F1                      *FFDD: F1       ; Data '.'
        FCB     $1C                      *FFDE: 1C       ; Data '.'
        FCB     $00                      *FFDF: 00       ; Data '.'
        FCB     $00                      *FFE0: 00       ; Data '.'
        FCB     $FF                      *FFE1: FF       ; Data '.'
        FCB     $7E                      *FFE2: 7E       ; Data '~'
        FCB     $81                      *FFE3: 81       ; Data '.'
        FCB     $F3                      *FFE4: F3       ; Data '.'
        FCB     $1C                      *FFE5: 1C       ; Data '.'
        FCB     $00                      *FFE6: 00       ; Data '.'
        FCB     $00                      *FFE7: 00       ; Data '.'
        FCB     $FF                      *FFE8: FF       ; Data '.'
        FCB     $01                      *FFE9: 01       ; Data '.'
        FCB     $00                      *FFEA: 00       ; Data '.'
        FCB     $F3                      *FFEB: F3       ; Data '.'
        FCB     $1C                      *FFEC: 1C       ; Data '.'
        FCB     $00                      *FFED: 00       ; Data '.'
        FCB     $00                      *FFEE: 00       ; Data '.'
        FCB     $FF                      *FFEF: FF       ; Data '.'
;
; Interrupt Vector table
;
svec_SWI4 FDB   hdlr_SWI4                *FFF0: FE E2    ; Serial I/O
svec_SWI3 FDB   hdlr_RST                 *FFF2: F0 00    ; Timer Overflow
svec_SWI2 FDB   hdlr_SWI2                *FFF4: FD 9D    ; Output Compare
svec_FIRQ FDB   hdlr_RST                 *FFF6: F0 00    ; Input Capture
svec_IRQ FDB    hdlr_RST                 *FFF8: F0 00    ; 6800 IRQ
svec_SWI FDB    hdlr_RST                 *FFFA: F0 00    ; 6800 SWI
svec_NMI FDB    hdlr_RST                 *FFFC: F0 00    ; 6800 NMI
svec_RST FDB    hdlr_RST                 *FFFE: F0 00    ; 6800 Reset

        END

The Paranoid

N/A